# US 2020/0401526 A1 · Streaming engine with early and late address and loop count registers to track architectural state

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- Number: US 2020/0401526 A1
- Document ID: US20200401526A1
- Status: Published application
- Kind: A1
- Application number: 16/916,254
- Filed: 2020-06-30
- Published: 2020-12-24
- Earliest claimed: 2016-12-20
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Joseph Zbiciak; Timothy D. Anderson
- Web page: https://patentgrep.com/patent/US20200401526A1

## CPC

- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 12/0862: with prefetch
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 13/1668: {Details of memory controller}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/10: Address translation
- G06F 2212/1016: Performance improvement
- G06F 2212/452: Instruction code
- G06F 2212/454: Vector or matrix data
- G06F 2212/6026: Prefetching based on access pattern detection, e.g. stride based prefetch
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

## Claims

### Claim 1

A device comprising:
a processing core;
a memory; and
a memory controller coupled to the processing core and to the memory, wherein the memory controller includes:
a first address generator configured to generate a first set of addresses;
a memory interface coupled to the memory and configured to retrieve a set of data based on the first set of addresses;
a buffer configured to store the set of data;
a second address generator configured to generate a second set of addresses that correspond to a subset of the set of data in the buffer; and
a holding register coupled to the processing core and configured to:
receive the subset of the set of data based on the second set of addresses from the buffer;
store the subset of the set of data; and
provide the subset of the set of data to the processing core.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first address generator includes:
a plurality of loop count registers;
a plurality of adders coupled to the plurality of loop count registers;
a plurality of comparators coupled to the plurality of adders and each configured to:
compare an output of a respective adder of the plurality of adders to a threshold; and
based on the output of the respective adder of the plurality of adders equaling the threshold, provide a loop end signal configured to cause an iteration of a next higher loop.

### Claim 3 (depends on 2)

The device of claim 2, wherein:
the first address generator includes a plurality of registers configured to store the thresholds for the plurality of comparators; and
the thresholds are based on a stream definition template.

### Claim 4 (depends on 2)

The device of claim 2, wherein the first address generator includes:
a plurality of multipliers coupled to the plurality of adders and each configured to multiply the output of a respective adder of the plurality of adders by a data element size to determine an address of the first set of addresses.

### Claim 5 (depends on 2)

The device of claim 2, wherein:
the processing core has a debugger function; and
values of the plurality of loop count registers are accessible by the processing core via the debugger function.

### Claim 6 (depends on 1)

The device of claim 1 further comprising an address register coupled to the first address generator and the memory interface and configured to store a first address of the first set of addresses that corresponds to a next data element to be retrieved from the memory by the memory interface.

### Claim 7 (depends on 1)

The device of claim 1, wherein the memory includes a level two (L2) cache and the memory interface is configured to retrieve the set of data directly from the L2 cache.

### Claim 8 (depends on 1)

The device of claim 1 comprising a level one (L1) cache and a level two (L2) cache, wherein:
the memory includes the L2 cache; and
the memory interface is configured to retrieve the set of data from the L2 cache via a data path that does not include the L1 cache.

### Claim 9 (depends on 1)

The device of claim 1, wherein the memory controller includes a data formatting circuit coupled between the buffer and the holding register and configured to format the subset of the set of data such that the formatted subset of the set of data is stored in the holding register.

### Claim 10 (depends on 9)

The device of claim 9, wherein the data formatting circuit is configured to format the subset of the set of data according to a stream definition template.

### Claim 11 (depends on 9)

The device of claim 9 further comprising a reference queue coupled to the data formatting circuit and configured to store, for each element of the set of data:
an address at which the element is stored in the buffer; and
a format for the element to be applied by the data formatting circuit.

### Claim 12 (depends on 1)

The device of claim 1, wherein the buffer is a first-in-first-out buffer.

### Claim 13

A device comprising:
a processing core;
a level one (L1) cache memory;
a level two (L2) cache memory; and
a memory controller coupled to the processing core and to the L2 cache memory, wherein the memory controller includes:
a first address generator configured to generate a first set of addresses;
a memory interface coupled to the L2 cache memory and configured to retrieve a set of data based on the first set of addresses from the L2 cache memory via a data path that does not include the L1 cache memory;
a buffer configured to store the set of data;
a second address generator configured to generate a second set of addresses that correspond to the set of data in the buffer; and
a holding register coupled to the processing core and configured to:
receive a subset of the set of data based on the second set of addresses from the buffer;
store the subset of the set of data; and
provide the subset of the set of data to the processing core.

### Claim 14 (depends on 13)

The device of claim 13, wherein the first address generator includes:
a plurality of loop count registers;
a plurality of adders coupled to the plurality of loop count registers;
a plurality of comparators coupled to the plurality of adders and each configured to:
compare an output of a respective adder of the plurality of adders to a threshold; and
based on the output of the respective adder of the plurality of adders equaling the threshold, provide a loop end signal configured to cause an iteration of a next higher loop.

### Claim 15 (depends on 14)

The device of claim 14, wherein:
the first address generator includes a plurality of registers configured to store the thresholds for the plurality of comparators; and
the thresholds are based on a stream definition template.

### Claim 16 (depends on 15)

The device of claim 15, wherein the first address generator includes:
a plurality of multipliers coupled to the plurality of adders and each configured to multiply the output of a respective adder of the plurality of adders by a data element size to determine an address of the first set of addresses.

### Claim 17 (depends on 14)

The device of claim 14, wherein:
the processing core has a debugger function; and
values of the plurality of loop count registers are accessible by the processing core via the debugger function.

### Claim 18 (depends on 13)

The device of claim 13, wherein the memory controller includes a data formatting circuit coupled between the buffer and the holding register and configured to format the subset of the set of data such that the formatted subset of the set of data is stored in the holding register.

### Claim 19 (depends on 18)

The device of claim 18, wherein the data formatting circuit is configured to format the subset of the set of data according to a stream definition template.

### Claim 20 (depends on 18)

The device of claim 18 further comprising a reference queue coupled to the data formatting circuit and configured to store, for each element of the set of data:
an address at which the element is stored in the buffer; and
a format for the element to be applied by the data formatting circuit.