# US 2020/0401525 A1 · Storage System and Method for Enabling Host-Driven Regional Performance in Memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401525 A1 - Document ID: US20200401525A1 - Status: Published application - Kind: A1 - Application number: 16/444,418 - Filed: 2019-06-18 - Published: 2020-12-24 - Earliest claimed: 2019-06-18 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Ramanathan Muthiah; Ramkumar Ramamurthy; Judah Gamliel Hahn - Web page: https://patentgrep.com/patent/US20200401525A1 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 12/10: Address translation - G06F 12/121: using replacement algorithms - G06F 2212/1016: Performance improvement - G06F 2212/1021: Hit rate improvement - G06F 2212/1044: Space efficiency improvement - G06F 2212/657: Virtual address space management - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7205: Cleaning, compaction, garbage collection, erase control - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A storage system and method for enabling host-driven regional performance in memory are provided. In one embodiment, a method is provided comprising receiving a directive from a host device as to a preferred logical region of a non-volatile memory in a storage system; and based on the directive, modifying a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in a volatile memory of the storage system. Other embodiments are provided, such as modifying a garbage collection policy of the storage system based on information from the host device regarding a preferred logical region of the memory. ## Claims ### Claim 1 A method for enabling host-driven regional performance in memory, the method comprising: performing the following in a storage system comprising a non-volatile memory and a volatile memory: receiving a directive from a host device as to a preferred logical region of the non-volatile memory; and based on the directive, modifying a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in the volatile memory. ### Claim 2 (depends on 1) The method of claim 1, wherein modifying the caching policy comprises caching only those pages of the logical-to-physical address map that cover the preferred logical region. ### Claim 3 (depends on 1) The method of claim 1, wherein modifying the caching policy comprises caching more pages of the logical-to-physical address map that cover the preferred logical region than pages of the logical-to-physical address map that cover other logical regions. ### Claim 4 (depends on 1) The method of claim 1, wherein modifying the caching policy comprises giving a preference to avoid, during a swap in/out process, evicting pages of the logical-to-physical address map that cover the preferred logical region. ### Claim 5 (depends on 1) The method of claim 1, further comprising mapping the preferred logical region to one or more single level cell (SLC) blocks in the non-volatile memory. ### Claim at position 6 6-20. (canceled) ### Claim 21 (depends on 1) The method of claim 1, wherein the non-volatile memory comprises a three-dimensional memory. ### Claim 22 A storage system comprising: a non-volatile memory; a volatile memory: and a controller configured to: receive an indication from a host as to a preferred logical region of the non-volatile memory; and based on the indication, change a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in the volatile memory. ### Claim 23 (depends on 22) The storage system of claim 22, wherein changing the caching policy comprises caching only those pages of the logical-to-physical address map that cover the preferred logical region. ### Claim 24 (depends on 22) The storage system of claim 22, wherein changing the caching policy comprises caching more pages of the logical-to-physical address map that cover the preferred logical region than pages of the logical-to-physical address map that cover other logical regions. ### Claim 25 (depends on 22) The storage system of claim 22, wherein changing the caching policy comprises giving a preference to avoid, during a swap in/out process, evicting pages of the logical-to-physical address map that cover the preferred logical region. ### Claim 26 (depends on 22) The storage system of claim 22, wherein the controller is further configured to map the preferred logical region to one or more single level cell (SLC) blocks in the non-volatile memory. ### Claim 27 (depends on 22) The storage system of claim 22, wherein the non-volatile memory comprises a three-dimensional memory. ### Claim 28 A storage system comprising: a non-volatile memory; a volatile memory: means for receiving an instruction from a host device as to a preferred logical area of the non-volatile memory; and means for modifying, based on the instruction, a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in the volatile memory. ### Claim 29 (depends on 28) The storage system of claim 28, wherein modifying the caching policy comprises caching only those pages of the logical-to-physical address map that cover the preferred logical area. ### Claim 30 (depends on 28) The storage system of claim 28, wherein modifying the caching policy comprises caching more pages of the logical-to-physical address map that cover the preferred logical area than pages of the logical-to-physical address map that cover other logical areas. ### Claim 31 (depends on 28) The storage system of claim 28, wherein modifying the caching policy comprises giving a preference to avoid, during a swap in/out process, evicting pages of the logical-to-physical address map that cover the preferred logical area. ### Claim 32 (depends on 28) The storage system of claim 28, further comprising means for mapping the preferred logical area to one or more single level cell (SLC) blocks in the non-volatile memory. ### Claim 33 (depends on 28) The storage system of claim 28, wherein the non-volatile memory comprises a three-dimensional memory. ### Claim 34 (depends on 28) The storage system of claim 28, wherein the means for receiving and the means for modifying comprise a controller. ### Claim 35 (depends on 28) The storage system of claim 28, wherein the storage system is integrated in the host device.