# US 2020/0401523 A1 · Prefetching in a lower level exclusive cache hierarchy > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401523 A1 - Document ID: US20200401523A1 - Status: Published application - Kind: A1 - Application number: 16/543,503 - Filed: 2019-08-16 - Published: 2020-12-24 - Earliest claimed: 2019-06-24 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Vikas SINHA; Teik TAN; Tarun NAKRA - Web page: https://patentgrep.com/patent/US20200401523A1 ## CPC - G06F 12/0862: with prefetch - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)} - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 2212/1021: Hit rate improvement - G06F 2212/1024: Latency reduction - G06F 2212/152: Virtualized environment, e.g. logically partitioned system - G06F 2212/507: using speculative control - G06F 2212/602: Details relating to cache prefetching - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to one general aspect, an apparatus may include a multi-tiered cache system that includes at least one upper cache tier relatively closer, hierarchically, to a processor and at least one lower cache tier relatively closer, hierarchically, to a system memory. The apparatus may include a memory interconnect circuit hierarchically between the multi-tiered cache system and the system memory. The apparatus may include a prefetcher circuit coupled with a lower cache tier of the multi-tiered cache system, and configured to issue a speculative prefetch request to the memory interconnect circuit for data to be placed into the lower cache tier. The memory interconnect circuit may be configured to cancel the speculative prefetch request if the data exists in an upper cache tier of the multi-tiered cache system. ## Claims ### Claim 1 An apparatus comprising: a multi-tiered cache system, comprising at least one upper cache tier relatively closer, hierarchically, to a processor and at least one lower cache tier relatively closer, hierarchically, to a system memory; a memory interconnect circuit hierarchically between the multi-tiered cache system and the system memory; and a prefetcher circuit coupled with a lower cache tier of the multi-tiered cache system, and configured to issue a speculative prefetch request to the memory interconnect circuit for data to be placed into the lower cache tier, and wherein the memory interconnect circuit is configured to cancel the speculative prefetch request if the data exists in an upper cache tier of the multi-tiered cache system. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the lower cache tier is an exclusive cache. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the memory interconnect circuit comprises a snoop filter directory, and wherein the memory interconnect circuit is configured to determine if the data exists in an upper cache tier of the multi-tiered cache system based, at least in part, upon the snoop filter directory. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the memory interconnect circuit is configured to transmit a cancelled prefetch response to the prefetcher circuit if the speculative prefetch request is cancelled. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the memory interconnect circuit is configured to cancel the speculative prefetch request if the speculative prefetch request is duplicative of another request for the data. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the apparatus includes a primary prefetcher circuit coupled with an upper cache tier, and wherein the primary prefetcher circuit is configured to issue non-speculative prefetch requests to at least the multi-tiered cache system and, if unfulfilled by the multi-tier cache system, through to the system memory. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the prefetcher circuit is configured to not have visibility into the contents of an upper cache tier, such that the prefetcher circuit is unaware whether the data is stored in the upper cache tier before issuing the speculative prefetch request. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the multi-tier cache system comprises a first and a second upper cache tiers, and a third lower cache tier. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the memory interconnect circuit is configured to cancel the speculative prefetch request before the speculative prefetch is forwarded to the system memory. ### Claim 10 An apparatus comprising: one or more processor cores, wherein each core comprises: a multi-tiered cache system, comprising at least one upper cache tier relatively closer, hierarchically, to a core's executing unit and at least one lower cache tier relatively closer, hierarchically, to a system memory, and a prefetcher circuit coupled with a lower cache tier of the respective multi-tiered cache system, and configured to issue a speculative prefetch request for data, wherein for each request for data the respective multi-tiered cache system is a requesting respective multi-tiered cache system and the respective prefetcher circuit is a requesting prefetcher circuit; and a memory interconnect circuit, hierarchically between the processor cores and the system memory, wherein the memory interconnect circuit is configured to cancel the speculative prefetch request if the data exists in an upper cache tier of the requesting multi-tiered cache system. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the lower cache tier is an exclusive cache. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein the memory interconnect circuit comprises a snoop filter directory, and wherein the memory interconnect circuit is configured to determine if the data exists in an upper cache tier of the requesting multi-tiered cache system based, at least in part, upon the snoop filter directory. ### Claim 13 (depends on 10) The apparatus of claim 10, wherein the memory interconnect circuit is configured to transmit a cancelled prefetch response to the prefetcher circuit if the speculative prefetch request is cancelled. ### Claim 14 (depends on 10) The apparatus of claim 10, wherein the memory interconnect circuit is configured to cancel the speculative prefetch request if the speculative prefetch request is duplicative of another request for the data. ### Claim 15 (depends on 10) The apparatus of claim 10, wherein each processor core includes a primary prefetcher circuit coupled with an upper cache tier, and wherein the primary prefetcher circuit is configured to issue non-speculative prefetch requests to at least the multi-tiered cache system and, if unfulfilled by the multi-tier cache system, through to the system memory. ### Claim 16 (depends on 10) The apparatus of claim 10, wherein the prefetcher circuit is configured to not have viability into the contents of an upper cache tier, such that the prefetcher circuit is unaware whether the data is stored in the upper cache tier before issuing the speculative prefetch request. ### Claim 17 (depends on 10) The apparatus of claim 10, wherein each multi-tier cache system comprises a first and a second upper cache tiers, and a third lower cache tier. ### Claim 18 (depends on 10) The apparatus of claim 10, wherein the memory interconnect circuit is configured to cancel the speculative prefetch request before the speculative prefetch is forwarded to the system memory. ### Claim 19 A system comprising: a computer processor, comprising one or more processor cores, wherein each core comprises: a multi-tiered cache system, comprising at least one upper cache tier relatively closer, hierarchically, to a core's executing unit and at least one lower cache tier relatively closer, hierarchically, to a system memory, and a prefetcher circuit coupled with a lower cache tier of the respective multi-tiered cache system, and configured to issue a speculative prefetch request for data, wherein for each request for data the respective multi-tiered cache system is a requesting respective multi-tiered cache system and the respective prefetcher circuit is a requesting prefetcher circuit; a memory interconnect circuit, hierarchically between the processor cores and the system memory, wherein the memory interconnect circuit is configured to cancel the speculative prefetch request if the data exists in an upper cache tier of the requesting multi-tiered cache system; and the system memory configured to store data. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the memory interconnect circuit comprises a snoop filter directory, and wherein the memory interconnect circuit is configured to determine if the data exists in an upper cache tier of the requesting multi-tiered cache system based, at least in part, upon the snoop filter directory.