# US 2020/0401520 A1 · Memory cache-line bounce reduction for shared i/o ring structures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401520 A1 - Document ID: US20200401520A1 - Status: Published application - Kind: A1 - Application number: 16/444,629 - Filed: 2019-06-18 - Published: 2020-12-24 - Earliest claimed: 2019-06-18 - Assignees: Red Hat, Inc. - Applicants: Red Hat, Inc. - Inventors: Michael Tsirkin - Web page: https://patentgrep.com/patent/US20200401520A1 ## CPC - G06F 5/06: for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} - G06F 12/084: with a shared cache - G06F 9/5061: {Partitioning or combining of resources} - G06F 2212/1008: Correctness of operation, e.g. memory ordering - G06F 2212/1024: Latency reduction - G06F 2212/152: Virtualized environment, e.g. logically partitioned system - G06F 2212/608: Details relating to cache mapping - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system includes a memory, a producer processor and a consumer processor. The memory includes a shared ring buffer, which has a partially overlapping active ring and processed ring. The producer processor is in communication with the memory and is configured to receive a request associated with a memory entry, store the request in a first slot of the shared ring buffer at a first offset, receive another request associated with another memory entry, and store the other request in a second slot (in the overlapping region adjacent to the first slot) of the shared ring buffer. The consumer processor is in communication with the memory and is configured to process the request and write the processed request in a third slot (outside of the overlapping region at a second offset and in a different cache-line than the second slot) of the shared ring buffer. ## Claims ### Claim 1 A system comprising: a memory including a shared ring buffer, wherein the shared ring buffer includes an active ring buffer and a processed ring buffer that partially overlap in an overlapping region, the active ring buffer having a first plurality of slots and the processed ring buffer having a second plurality of slots; a producer processor configured to: receive a first request associated with a first memory entry, store the first request in a first slot of the shared ring buffer at a first offset, receive a second request associated with a second memory entry, store the second request in a second slot of the shared ring buffer, wherein the second slot is located in the overlapping region and adjacent to the first slot; and a consumer processor configured to process the first request and write the processed first request in a third slot of the shared ring buffer at a second offset, wherein the third slot is located in the processed ring buffer outside of the overlapping region, and the third slot is in a different cache-line than the second slot. ### Claim 2 (depends on 1) The system of claim 1, wherein the shared ring buffer includes a starting slot, a set of overlapping slots in the overlapping region, and an end slot. ### Claim 3 (depends on 2) The system of claim 2, wherein the set of overlapping slots includes an initial slot and a final slot. ### Claim 4 (depends on 3) The system of claim 3, wherein the initial slot is the first slot and the starting slot is the third slot. ### Claim 5 (depends on 1) The system of claim 1, wherein the consumer processor and the producer processor are on different cores of the same physical processor. ### Claim 6 (depends on 1) The system of claim 1, wherein the consumer processor and the producer processor are different physical processors. ### Claim 7 (depends on 1) The system of claim 1, wherein the shared ring buffer occupies a non-integer number of cache-lines. ### Claim 8 (depends on 1) The system of claim 1, wherein the shared ring buffer occupies an integer number of cache-lines. ### Claim 9 (depends on 1) The system of claim 1, wherein the first request is a packet address. ### Claim 10 (depends on 1) The system of claim 1, wherein the producer processor is configured to maintain a spacing from the consumer processor, wherein the spacing includes a set of consecutive slots, wherein the set of consecutive slots occupies at least one entire cache-line. ### Claim 11 (depends on 1) The system of claim 1, wherein the consumer processor is configured to maintain a spacing from the producer processor, wherein the spacing includes a set of consecutive slots, wherein the set of consecutive slots occupies at least one entire cache-line. ### Claim 12 (depends on 1) The system of claim 1, wherein the producer processor is allowed to store a request in the first plurality of slots and is restricted from storing the request in slots of the second plurality of slots outside of the overlapping region. ### Claim 13 (depends on 1) The system of claim 1, wherein the consumer processor is allowed write a processed request in the second plurality of slots and is restricted from writing the processed request in slots of the first plurality of slots outside of the overlapping region. ### Claim 14 A method comprising: receiving, by a producer processor, a first request associated with a first memory entry; storing, by the producer processor, the first request in a first slot of a shared ring buffer at a first offset, wherein the shared ring buffer includes an active ring buffer and a processed ring buffer that partially overlap in an overlapping region, the active ring buffer having a first plurality of slots and the processed ring buffer having a second plurality of slots; processing, by a consumer processor, the first request; writing, by the consumer processor, the processed first request in a second slot of the shared ring buffer at a second offset, wherein the second slot is located in the processed ring buffer outside of the overlapping region; receiving, by the producer processor, a second request associated with a second memory entry; and storing, by the producer processor, the second request in a third slot of the shared ring buffer, wherein the third slot is located in the overlapping region and adjacent to the first slot, and the third slot is in a different cache-line than the second slot. ### Claim 15 (depends on 14) The method of claim 14, further comprising: maintaining, by the producer processor, a spacing from the consumer processor, wherein the spacing includes a set of slots, wherein the set of slots occupies at least one entire cache-line. ### Claim 16 (depends on 14) The method of claim 14, further comprising: maintaining, by the consumer processor, a spacing from the producer processor, wherein the spacing includes a set of slots, wherein the set of slots occupies at least one entire cache-line. ### Claim 17 A system comprising: a memory including a shared ring buffer having a plurality of slots, wherein the shared ring buffer includes an active ring buffer and a processed ring buffer that entirely overlap; a producer processor configured to: receive a first request associated with a first memory entry, store the first request in a first slot of the shared ring buffer, receive a second request associated with a second memory entry, store the second request in a second slot adjacent to the first slot; and a consumer processor configured to process the first request and write the processed first request in the shared ring buffer in a third slot at an offset, wherein the offset and the location of the first slot create a spacing between slots successively accessed by the consumer processor and the producer processor, wherein the third slot is in a different cache-line than the second slot. ### Claim 18 (depends on 17) The system of claim 17, further comprising a counter that is configured to track a position of a current slot accessed by the consumer processor. ### Claim 19 (depends on 18) The system of claim 18, wherein the consumer processor is configured to wrap around the shared ring buffer to the starting slot when a counter value tracked by the counter exceeds the size of the shared ring buffer. ### Claim 20 (depends on 17) The system of claim 17, further comprising a counter that is configured to track a position of a current slot accessed by the producer processor, and the producer processor is configured to wrap around the shared ring buffer to the starting slot when a counter value tracked by the counter exceeds the size of the shared ring buffer.