# US 2020/0401519 A1 · Region based split-directory scheme to adapt to large cache sizes

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- Number: US 2020/0401519 A1
- Document ID: US20200401519A1
- Status: Published application
- Kind: A1
- Application number: 16/919,638
- Filed: 2020-07-02
- Published: 2020-12-24
- Earliest claimed: 2018-08-31
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Vydhyanathan Kalyanasundharam; Kevin M. Lepak; Amit P. Apte; Ganesh Balakrishnan
- Web page: https://patentgrep.com/patent/US20200401519A1

## CPC

- G06F 12/082: {Associative directories (G06F12/0822 takes precedence)}
- G06F 12/0824: {Distributed directories, e.g. linked lists of caches}
- G06F 12/0826: {Limited pointers directories; State-only directories without pointers}
- G06F 2212/622: State-only directory, i.e. not recording identity of sharing or owning nodes
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A system comprising:
a plurality of processing nodes, wherein each processing node comprises one or more processors and a cache subsystem;
one or more node-based cache directories configured to track which regions of a memory have at least one cache line cached in a cache subsystem of a given processing node, wherein a region comprises a plurality of cache lines; and
one or more memory-based cache directories configured to track which regions of a corresponding memory address range having entries in any of the plurality of node-based cache directories;
wherein a first memory-based cache directory is configured to:
maintain an entry for each region of a first memory address range that also has an entry in at least one node-based cache directory; and
invalidate an entry in the memory-based cache directory, based at least in part on all corresponding entries in the node-based cache directories being invalidated.

### Claim 22 (depends on 21)

The system as recited in claim 21, wherein the first memory-based cache directory is configured to invalidate the entry in the memory-based cache directory responsive to receiving a notification from a node-based cache directory that indicates a corresponding entry in the node-based cache directory has been invalidated.

### Claim 23 (depends on 22)

The system as recited in claim 22, wherein the first memory-based cache directory is configured to invalidate the entry in the memory-based cache directory in further response to determining that no other node-based cache directory has an entry corresponding to the entry in the memory-based cache directory.

### Claim 24 (depends on 21)

The system as recited in claim 21, wherein each node-based cache directory is configured to maintain an entry for each region of memory which has at least one cache line cached in a corresponding processing node.

### Claim 25 (depends on 24)

The system as recited in claim 24, wherein a first node-based cache directory is configured to track a number of cache lines of a corresponding memory region that are cached in any cache subsystem of a node that corresponds to the first node-based cache directory.

### Claim 26 (depends on 21)

The system as recited in claim 21, wherein the first memory-based cache directory is further configured to maintain a bit that indicates a node-based cache directory has a valid entry corresponding to a valid entry in the first memory-based cache directory.

### Claim 27 (depends on 26)

The system as recited in claim 26, wherein the first memory-based cache directory is further configured to invalidate the valid entry in the first memory-based cache directory responsive to the bit being cleared.

### Claim 28

A method comprising:
tracking, by a node-based cache directory of a plurality of node-based cache directories, which regions of memory have at least one cache line cached in a cache subsystem of a corresponding processing node, wherein a region comprises a plurality of cache lines;
maintaining, by a first memory-based cache directory, an entry for each region of a first memory address range that also has an entry in at least one node-based cache directory; and
invalidating, by the first memory-based cache directory, an entry in the memory-based cache directory, based at least in part on all corresponding entries in the node-based cache directories being invalidated.

### Claim 29 (depends on 28)

The method as recited in claim 28, further comprising invalidating, by the first memory-based cache directory, the entry in the memory-based cache directory responsive to receiving a notification from a node-based cache directory that indicates a corresponding entry in the node-based cache directory has been invalidated.

### Claim 30 (depends on 29)

The method as recited in claim 29, further comprising invaliding, by the first memory-based cache directory, the entry in the memory-based cache directory in further response to determining that no other node-based cache directory has an entry corresponding to the entry in the memory-based cache directory.

### Claim 31 (depends on 28)

The method as recited in claim 28, further comprising maintaining, by each node-based cache directory, an entry for each region of memory which has at least one cache line cached in a corresponding processing node.

### Claim 32 (depends on 31)

The method as recited in claim 31, further comprising tracking, by a first node-based cache directory, a number of cache lines of a corresponding memory region that are cached in any cache subsystem of a node that corresponds to the first node-based cache directory.

### Claim 33 (depends on 28)

The method as recited in claim 28, further comprising maintaining, by the first memory-based cache directory, a bit that indicates a node-based cache directory has a valid entry corresponding to a valid entry in the first memory-based cache directory.

### Claim 34 (depends on 33)

The method as recited in claim 33, further comprising invalidating the valid entry in the first memory-based cache directory responsive to the bit being cleared.

### Claim 35

An apparatus comprising:
a plurality of entries; and
circuitry configured to:
track which regions of a corresponding memory address range have entries in any of a plurality of node-based cache directories;
maintain an entry of the plurality of entries for each region of a first memory address range that also has a valid entry in at least one node-based cache directory of the plurality of node-based cache directories; and
invalidate an entry of the plurality of entries, based at least in part on all corresponding entries in the plurality of node-based cache directories being invalidated.

### Claim 36 (depends on 35)

The apparatus as recited in claim 35, wherein each entry of the plurality of entries is configured to store an indication for each of a plurality of processors in a system.

### Claim 37 (depends on 36)

The apparatus as recited in claim 36, wherein each said indication indicates whether a corresponding processor has a valid entry corresponding to an entry in the plurality of entries.

### Claim 38 (depends on 35)

The apparatus as recited in claim 35, wherein each entry of the plurality of entries is further configured to store coherency state.

### Claim 39 (depends on 38)

The apparatus as recited in claim 38, wherein the circuitry is configured to set the coherency state to a most restrictive coherency state of a plurality of cache lines that correspond to a memory region.

### Claim 40 (depends on 19)

The apparatus as recited in claim 19, wherein the circuitry is configured to the entry responsive to receiving an invalidation notification from a node-based cache directory.