# US 2020/0401518 A1 · Memory controller and memory system having the memory controller > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401518 A1 - Document ID: US20200401518A1 - Status: Published application - Kind: A1 - Application number: 16/698,244 - Filed: 2019-11-27 - Published: 2020-12-24 - Earliest claimed: 2019-06-24 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jeen PARK - Web page: https://patentgrep.com/patent/US20200401518A1 ## CPC - G06F 12/0653: {with centralised address assignment} - G11C 7/1042: {using interleaving techniques, i.e. read-write of one part of the memory while preparing another part} - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G06F 2212/1016: Performance improvement - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant - G11C 2216/14: Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract There are provided a memory controller for performing a program operation and a memory system having the memory controller. The memory system includes a memory device including first and second planes each including a plurality of m-bit (m is a natural number of 2 or more) multi-level cell (MLC) blocks; and a memory controller for allocating a first address corresponding to a first MLC block of the m-bit MLC blocks in which first m-bit MLC data is to be programmed and a second address corresponding to a second MLC block of the m-bit MLC blocks in which second m-bit MLC data is to be programmed, and transmitting the allocated addresses and logical page data included in the m-bit MLC data to the memory device. The memory controller differently determines a transmission sequence of the logical page data according to whether the addresses correspond to the same plane among the planes. ## Claims ### Claim 1 A memory system comprising: a memory device including first and second planes each including a plurality of M-bit multi-level cell (MLC) blocks, where M is a natural number of 2 or more; and a memory controller configured to: allocate a first address corresponding to a first MLC block of the M-bit MLC blocks, in which first M-bit MLC data is to be programmed and a second address corresponding to a second MLC block of the M-bit MLC blocks, in which second M-bit MLC data is to be programmed, and transmit the allocated addresses and plural pieces of logical page data included in the first and second M-bit MLC data to the memory device, wherein the memory controller is further configured to differently determine a transmission sequence of the plural pieces of logical page data for the transmission according to whether the first and second addresses correspond to a same plane in the memory device. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the memory controller includes: a first buffer configured to store program data received from a host, the program data including the first and second M-bit MLC data; an address allocator configured to allocate the first and second addresses; a second buffer configured to output the plural pieces of logical page data to the memory device according to the transmission sequence; and a data sequence manager configured to determine the transmission sequence, and queue the plural pieces of logical page data in the second buffer according to the transmission sequence. ### Claim 3 (depends on 2) The memory system of claim 2, wherein, upon a determination that the first and second addresses correspond to the same plane, the data sequence manager is configured to determine the transmission sequence such that plural pieces of logical page data included in the first M-bit MLC data is transmitted prior to plural pieces of logical page data included in the second M-bit MLC data. ### Claim 4 (depends on 3) The memory system of claim 3, wherein the data sequence manager is configured to determine, with respect to M pieces of logical page data included in each of the first and second M-bit MLC data, the transmission sequence such that a piece of logical page data corresponding to a lower-level logical page is transmitted prior to a piece of logical page data corresponding to a higher-level logical page. ### Claim 5 (depends on 2) The memory system of claim 2, wherein, upon a determination that the first and second addresses correspond to different planes, the data sequence manager is configured to determine, with respect to 2 groups of M pieces of logical page data included in the first and second M-bit MLC data, the transmission sequence of a piece of logical page data corresponding to a lower-level logical page is transmitted prior to a piece of logical page data corresponding to a higher-level logical page. ### Claim 6 (depends on 2) The memory system of claim 2, wherein the second buffer is configured to output the first and second addresses to the memory device according to a sequence in which the addresses are queued, wherein the data sequence manager is configured to queue the first address in the second buffer prior to the second address. ### Claim 7 (depends on 1) The memory system of claim 1, wherein the memory device includes: a first multi-level buffer corresponding to the first plane; a second multi-level buffer corresponding to the second plane; an input/output circuit configured to receive the first and second addresses and the plural pieces of logical page data from the memory controller; and a control logic configured to store the plural pieces of logical page data in at least one of the first and second multi-level buffers according to the first and second addresses transferred from the input/output circuit. ### Claim 8 (depends on 7) The memory system of claim 7, wherein, upon a determination that the first and second addresses correspond to the first plane, the control logic is configured to sequentially store the received plural pieces of logical page data in the first multi-level buffer. ### Claim 9 (depends on 8) The memory system of claim 8, wherein the control logic is configured to: program previous M pieces of the plural pieces of logical page data sequentially stored in the first multi-level buffer to a single physical page included in the first MLC block corresponding to the first address; and program subsequent M pieces of the plural pieces of logical page data sequentially stored in the first multi-level buffer to a single physical page included in the second MLC block corresponding to the second address. ### Claim 10 (depends on 7) The memory system of claim 7, wherein, upon a determination that the first address corresponds to the first plane and the second address corresponds to the second plane, the control logic is configured to: store M pieces of logical page data received in an odd-numbered order among the plural pieces of logical page data in the first multi-level buffer; and store M pieces of logical page data received in an even-numbered order among the plural pieces of logical page data in the second multi-level buffer. ### Claim 11 (depends on 10) The memory system of claim 10, wherein the control logic is configured to: program the M pieces of logical page data stored in the first multi-level buffer to one physical page included in the first MLC block corresponding to the first address; and program the M pieces of logical page data stored in the second multi-level buffer to one physical page included in the second MLC block corresponding to the second address. ### Claim 12 A memory controller comprising: a first buffer configured to store program data received from a host; a data divider configured to divide the program data into first and second M-bit MLC data each including M pieces of logical page data, where M is a natural number of 2 or more; an address allocator configured to allocate a first address corresponding to a first MLC block in which the first M-bit MLC data is to be programmed among a plurality of M-bit MLC blocks included in a memory device and a second address corresponding to a second MLC block in which the second M-bit MLC data is to be programmed among the plurality of M-bit MLC blocks; a second buffer configured to output the M pieces of logical page data to the memory device according to a transmission sequence in which the M pieces of logical page data included in the first and second M-bit MLC data are queued; and a data sequence manager configured to differently determine the transmission sequence according to whether the first and second addresses correspond to a same plane included in the memory device, and queue the M pieces of logical page data in the second buffer according to the transmission sequence. ### Claim 13 (depends on 12) The memory controller of claim 12, wherein the second buffer is configured to output the first and second addresses to the memory device according to a sequence in which the addresses are queued, wherein the data sequence manager is configured to queue the first address in the second buffer prior to the second address. ### Claim 14 (depends on 12) The memory controller of claim 12, wherein, upon a determination that the first and second addresses correspond to the same plane, the data sequence manager is configured to determine the transmission sequence such that M pieces of logical page data included in the first M-bit MLC data is transmitted prior to M pieces of logical page data included in the second M-bit MLC data. ### Claim 15 (depends on 14) The memory controller of claim 14, wherein the data sequence manager is configured to determine, with respect to M pieces of logical page data included in each of the first and second M-bit MLC data, the transmission sequence such that a piece of logical page data corresponding to a lower-level logical page is transmitted prior to a piece of logical page data corresponding to a higher-level logical page. ### Claim 16 (depends on 12) The memory controller of claim 12, wherein, upon a determination that the first and second addresses correspond to different planes, the data sequence manager is configured to determine, with respect to 2 groups of M pieces of logical page data included in the first and second M-bit MLC data, the transmission sequence such that a piece of logical page data corresponding to a lower-level logical page is transmitted prior to a piece of logical page data corresponding to a higher-level logical page. ### Claim 17 An operating method of a controller for controlling a memory device including a plane having N number of M-bit multi-level cell (MLC) blocks, the method comprising: arranging N groups of M pieces of logical page data by units of the N groups and in an ascending order of logical levels of the logical page data within each of the N groups, the M pieces respectively corresponding to the logical levels; and controlling the memory device to sequentially store the arranged logical page data by units of the N groups into the MLC blocks.