# US 2020/0401515 A1 · Garbage collection adapted to user device access > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401515 A1 - Document ID: US20200401515A1 - Status: Published application - Kind: A1 - Application number: 16/445,816 - Filed: 2019-06-19 - Published: 2020-12-24 - Earliest claimed: 2019-06-19 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Qing Liang; Deping He; David Aaron Palmer - Web page: https://patentgrep.com/patent/US20200401515A1 ## CPC - G06F 12/0253: {Garbage collection, i.e. reclamation of unreferenced memory} - G11C 16/32: Timing circuits - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G11C 11/1659: {Cell access} - G11C 16/10: Programming or data input circuits - G06F 2212/7205: Cleaning, compaction, garbage collection, erase control - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Systems and methods for adapting garbage collection (GC) operations in a memory device to a pattern of host accessing the device are discussed. The host access pattern can be represented by how frequent the device is in idle states free of active host access. An exemplary memory device includes a memory controller to track a count of idle periods during a specified time window, and to adjust an amount of memory space to be freed by a GC operation in accordance with the count of idle periods. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the count of idle periods during the specified time window. ## Claims ### Claim 1 A memory device, comprising: a group of memory cells; and a memory controller, including: a user device access tracker circuit configured to detect an idle period during which the memory device is free of active access by a host, and to track a count of idle periods detected during a specified time window; and a garbage collection (GC) controller configured to adjust an amount of memory space to be freed by a GC operation on a portion of the memory cells according to the count of idle periods. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the GC controller is configured to: increase the amount of memory space to be freed by a GC operation when the count of idle periods is below an idle period count threshold; and withhold the GC operation or decrease the amount of memory space to be freed by a GC operation when the count of idle periods is above the idle period count threshold. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the GC controller is configured to generate a control signal to initiate a discretionary GC operation when there is free memory space in the device memory available for host write. ### Claim 4 (depends on 1) The memory device of claim 1, wherein: the user device access tracker circuit is further configured to detect an active host access periods during the specified time window; and the GC controller is configured to adjust an amount of memory space to be freed by a GC operation further using the detected active host access periods. ### Claim 5 (depends on 4) The memory device of claim 4, wherein: the user device access tracker circuit is configured to track a count of transitions between the active host access periods and the idle periods during the specified time window; and the GC controller is configured to increase the amount of memory space to be freed by a GC operation when the count of transitions is below a state transition count threshold, and to withhold the GC operation or decrease the amount of memory space to be freed by a GC operation when the count of transitions is above the state transition count threshold. ### Claim 6 (depends on 1) The memory device of claim 1, further comprising a single level cell (SLC) cache controller configured to adjust a size of an SLC cache, including a reallocation of a portion of the memory cells between the SLC cache and a multi-level cell (MLC) storage, according to the count of idle periods. ### Claim 7 (depends on 6) The memory device of claim 6, wherein the SLC cache controller is configured to: increase the SLC cache size, including reduce the reallocation of memory cells in the SLC cache to the MLC storage, when the count of idle periods is below an idle period count threshold; or reduce the SLC cache size, including increase the reallocation of memory cells in the SLC cache to the MLC storage when the count of idle periods is above an idle period count threshold. ### Claim 8 (depends on 6) The memory device of claim 6, wherein the memory cells allocated as the MLC storage store three or more bits of data per memory cell. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the user device access tracker circuit is configured to track the count of idle periods continuously or periodically. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the GC controller is configured to initiate or adjust the GC operation during a device idle state. ### Claim 11 (depends on 1) The memory device of claim 1, wherein the GC controller is configured to initiate a GC operation in response to a trigger event, the trigger event including at least one of: an actual device age exceeding an age threshold; an actual cumulative host write count exceeding a host byte count threshold; or an actual cumulative physical write count exceeding a physical byte count threshold. ### Claim 12 (depends on 1) The memory device of claim 1, wherein the memory device is a solid state drive (SSD) device including NAND flash memories. ### Claim 13 A method of optimizing memory utilization in a memory device via a memory controller, the method comprising: detecting an idle period during which the memory device is free of active access by a host; tracking a count of idle periods detected during a specified time window; and adjusting an amount of memory space to be freed by a garbage collection (GC) operation on a portion of the memory cells according to the count of idle periods. ### Claim 14 (depends on 13) The method of claim 13, comprising: increasing the amount of memory space to be freed by a GC operation when the count of idle periods is below an idle period count threshold; or withholding the GC operation or decreasing the amount of memory space to be freed by a GC operation when the count of idle periods is above the idle period count threshold. ### Claim 15 (depends on 13) The method of claim 13, comprising: detecting active host access periods during the specified time window; and adjusting an amount of memory space to be freed by a GC operation further using the detected active host access periods. ### Claim 16 (depends on 15) The method of claim 15, comprising: tracking a count of transitions between the active host access periods and the idle periods during the specified time window; and increasing the amount of memory space to be freed by a GC operation when the count of transitions is below a state transition count threshold, and withholding the GC operation or decreasing the amount of memory space to be freed by a GC operation when the count of transitions is above the state transition count threshold. ### Claim 17 (depends on 13) The method of claim 13, wherein the tracking the count of idle periods is performed continuously or periodically. ### Claim 18 (depends on 13) The method of claim 13, comprising adjusting a size of a single level cell (SLC) cache, including adjusting reallocation of a portion of the memory cells between the SLC cache and a multi-level cell (MLC) storage, according to the count of idle periods. ### Claim 19 (depends on 18) The method of claim 18, wherein adjusting the SLC cache size includes: increasing the SLC cache size, including reducing the reallocation of memory cells in the SLC cache to the MLC storage, when the count of idle periods is below an idle period count threshold; or reducing the SLC cache size, including increasing the reallocation of memory cells in the SLC cache to the MLC storage, when the count of idle periods is above an idle period count threshold. ### Claim 20 (depends on 13) The method of claim 13, comprising detecting a trigger event, and initiating a GC operation in response to the detection of the trigger event, the trigger event including at least one of: the actual device age exceeding an age threshold; an actual cumulative host write count exceeding a host byte count threshold; or an actual cumulative physical write count exceeding a physical byte count threshold.