# US 2020/0401513 A1 · Garbage collection adapted to host write activity

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- Number: US 2020/0401513 A1
- Document ID: US20200401513A1
- Status: Published application
- Kind: A1
- Application number: 16/445,738
- Filed: 2019-06-19
- Published: 2020-12-24
- Earliest claimed: 2019-06-19
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Deping He; Qing Liang; David Aaron Palmer
- Web page: https://patentgrep.com/patent/US20200401513A1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0253: {Garbage collection, i.e. reclamation of unreferenced memory}
- G06F 2212/1016: Performance improvement
- G06F 2212/1036: Life time enhancement
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7204: Capacity control, e.g. partitioning, end-of-life degradation
- G06F 2212/7205: Cleaning, compaction, garbage collection, erase control
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

## Claims

### Claim 1

A memory device, comprising:
a group of memory cells; and
a memory controller, including:
a workload tracker circuit configured to track a host write progress metric representing an actual host write count relative to a target host write count, the actual host write count representing an actual amount of data requested by a host to write to the memory cells during a specified time period, and the target host write count representing a target amount of data expected to be requested by the host to write to the memory cells during the same specified time period; and
a garbage collection (GC) controller configured to adjust an amount of memory space to be freed by a GC operation on a portion of the group of the memory cells according to the tracked host write progress metric.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the GC controller is configured to:
increase the amount of memory space to be freed by a GC operation if the actual host write count is less than the target host write count by a specified margin, and withhold a GC operation or decrease the amount of memory space to be freed by a GC operation if the actual host write count is greater than the target host write count by a specified margin; and
generate a control signal to initiate a discretionary GC operation when there is free memory space in the device memory available for host write.

### Claim 3 (depends on 1)

The memory device of claim 1, further comprising a single level cell (SLC) cache controller configured to adjust a size of an SLC cache, including reallocation of a portion of the memory cells between the SLC cache and a multi-level cell (MLC) storage, according to the tracked host write progress metric.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the SLC cache controller is configured to:
increase the SLC cache size, including reduce the reallocation of memory cells in the SLC cache to the MLC storage, if the actual host write count is less than the target host write count by a specified margin; or
reduce the SLC cache size, including increase the reallocation of memory cells in the SLC cache to the MLC storage, if the actual host write count is greater than the target host write count by a specified margin.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the memory cells allocated as the MLC storage store three or more bits of data per memory cell.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the actual host write count includes an actual daily host bytes written, and wherein the target host write count includes a target daily amount of data expected to be written to the memory device.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the actual host write count includes an actual cumulative host bytes written accumulated over a specified time period, and wherein the target host write count includes a target cumulative amount of data expected to be written to the memory device over the specified time period.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the actual host write count includes an estimate of host bytes written per program/erase (P/E) cycle, and wherein the target host write count includes a target amount of data expected to be written to the memory device per P/E cycle.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the actual host write count includes an actual cumulative host bytes written over a specified number of program/erase (P/E) cycles, and wherein the target host write count includes a target cumulative amount of data expected to be written to the memory device over the specified number of P/E cycles.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein:
the workload tracker circuit is configured to track an actual cumulative physical write count representing an amount of data physically written to the memory cells accumulated over a specified time period; and
the GC controller is configured to adjust the amount of memory space to be freed by a GC operation using the tracked actual cumulative physical write count relative to a target cumulative physical write count, the target cumulative physical write count representing an amount of data expected to be physically written to the memory cells over the specified time period.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the workload tracker circuit is configured to track host write progress metric continuously or periodically.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein the GC controller is configured to initiate a GC operation in response to a trigger event including at least one of:
the actual device age exceeding an age threshold;
an actual cumulative host write count exceeding a host bytes threshold; or
an actual cumulative physical write count exceeding a physical bytes threshold.

### Claim 13 (depends on 1)

The memory device of claim 1, wherein the memory device is a solid state drive (SSD) device including NAND flash memories.

### Claim 14

A method of optimizing memory utilization in a memory device via a memory controller, the method comprising:
tracking a host write progress metric representing an actual host write count relative to a target host write count, the actual host write count representing an actual amount of data requested by a host to write to memory cells of the memory device during a specified time period, and the target host write count representing a target amount of data expected to be requested by the host to write to the memory cells during the same specified time period; and
adjusting an amount of memory space to be freed by a garbage collection (GC) operation on a portion of the memory cells according to the tracked host write progress metric.

### Claim 15 (depends on 14)

The method of claim 14, comprising initiating a discretionary GC operation when there is free memory space in the device memory available for host write, wherein adjusting the GC operation includes:
increasing the amount of memory space to be freed by a GC operation if the actual host write count is less than the target host write count by a specified margin; or
withholding a GC operation or decreasing the amount of memory space to be freed by a GC operation if the actual host write count is greater than the target host write count by a specified margin.

### Claim 16 (depends on 14)

The method of claim 14, further comprising, according to the tracked host write progress metric, adjusting a size of a single level cell (SLC) cache including adjusting reallocation of a portion of the memory cells between the SLC cache and a multi-level cell (MLC) storage.

### Claim 17 (depends on 16)

The method of claim 16, wherein adjusting the SLC cache size includes:
increasing the SLC cache size, including reducing the reallocation of memory cells in the SLC cache to the MLC storage, if the actual host write count is less than the target host write count by a specified margin; or
reducing the SLC cache size, including increasing the reallocation of memory cells in the SLC cache to the MLC storage, if the actual host write count is greater than the target host write count by a specified margin.

### Claim 18 (depends on 14)

The method of claim 14, wherein the actual host write count and the target host write count are each determined by a unit time or a program/erase (P/E) cycle, or accumulated over a specified time period or a specified number of P/E cycles.

### Claim 19 (depends on 14)

The method of claim 14, comprising:
tracking an actual cumulative physical write count representing an amount of data physically written to the memory cells over a specified time period; and
adjusting the amount of memory space to be freed by a GC operation using the tracked actual cumulative physical write count relative to a target cumulative physical write count representing an amount of data expected to be physically written to the memory cells over the specified time period.

### Claim 20 (depends on 14)

The method of claim 14, comprising detecting a trigger event, and initiating a GC operation in response to the detection of the trigger event, the trigger event including at least one of:
the actual device age exceeding an age threshold;
an actual cumulative host write count exceeding a host bytes threshold; or
an actual cumulative physical write count exceeding a physical bytes threshold.