# US 2020/0401509 A1 · Apparatus and method and computer program product for handling flash physical-resource sets

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- Number: US 2020/0401509 A1
- Document ID: US20200401509A1
- Status: Published application
- Kind: A1
- Application number: 16/732,944
- Filed: 2020-01-02
- Published: 2020-12-24
- Earliest claimed: 2019-06-21
- Assignees: Silicon Motion, Inc.
- Applicants: Silicon Motion, Inc.
- Inventors: Che-Wei HSU
- Web page: https://patentgrep.com/patent/US20200401509A1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 3/061: {Improving I/O performance}
- G06F 3/064: {Management of blocks}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 12/0882: Page mode
- G06F 13/1673: {using buffers}
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7207: management of metadata or control data
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.

## Claims

### Claim 1

An apparatus for handling flash physical-resource sets, comprising:
a random access memory (RAM), comprising a plurality of segments of temporary space, wherein each segment of temporary space stores variables associated with a specific flash physical-resource set;
a processing unit, coupled to the RAM, arranged to operably access user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL); and
an address conversion circuit, coupled to the RAM, arranged to operably receive a memory address issued from the FTL, convert the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and output the relative address to the RAM for accessing a variable of the associated segment of temporary space.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the address conversion circuit comprises:
a set-selection register;
a multiplier, coupled to the set-selection register, arranged to operably time a value of the set-selection register by a total length of temporary space that is allocated for each flash physical-resource set to generate a calculation result; and
an adder, coupled to the multiplier, arranged to operably plus the calculation result to the memory address to generate the relative address and output the relative address to the RAM.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the address conversion circuit comprises:
an offset register, coupled to the multiplier, arranged to operably store the total length of temporary space that is allocated for each flash physical-resource set,
wherein the FTL sets a number corresponding to the associated flash physical-resource set to the set-selection register before accessing to the RAM.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the address conversion circuit comprises:
a set-selection register;
a plurality of address registers, wherein each address register is arranged to operably store a start address of the RAM that is associated with a specific flash physical-resource set;
an adder; and
a multiplexer, coupled to the set-selection register, the address registers and the adder, arranged to operably connect one of the address registers to the adder according to a control signal corresponding to a value of the set-selection register,
wherein the adder is arranged to operably plus the start address of the connected address register to the memory address to generate the relative address, and output the relative address to the RAM.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the FTL sets a number corresponding to the associated flash physical-resource set to the set-selection register before accessing to the RAM.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein each flash physical-resource set comprises a portion of channels and a portion of Logical Unit Numbers (LUNs).

### Claim 7 (depends on 1)

The apparatus of claim 1, comprising:
a flash interface, coupled to the processing unit,
wherein the FTL drives the flash interface to access user data of the flash physical-resource set according to the accessed variable.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the user data is accessed during a performance of an operation being associated with an I/O command read from a submission queue, or being a background operation irrelevant from a host.

### Claim 9

A method for handling flash physical-resource sets, performed by a processing unit when loading and executing program code of a flash translation layer, comprising:
during a performance of an operation, after writing a number corresponding to a physical-resource set into a set-selection register of an address conversion circuit, sending a memory address for a variable value to be read or written into the address conversion circuit, thereby enabling the address conversion circuit to convert the memory address into a relative address corresponding to allocated space for the physical-resource set and output the relative address to a random access memory (RAM); and reading the variable value from the relative address of the RAM, or writing the variable value into the relative address of the RAM.

### Claim 10 (depends on 9)

The method of claim 9, wherein the operation is associated with an I/O command read from a submission queue, or is a background operation irrelevant from a host.

### Claim 11 (depends on 9)

The method of claim 9, wherein the RAM comprises a plurality of segments of temporary space and each segment of temporary space stores variables associated with a specific flash physical-resource set.

### Claim 12 (depends on 9)

The method of claim 9, comprising:
during the performance of the operation, driving a flash interface to access user data of the physical-resource set according to the variable value.

### Claim 13

A non-transitory computer program product for handling flash physical-resource sets when executed by a processing unit, the non-transitory computer program product comprising program code of a flash translation layer (FTL) to:
during a performance of an operation, after writing a number corresponding to a physical-resource set into a set-selection register of an address conversion circuit, send a memory address for a variable value to be read or written into the address conversion circuit, thereby enabling the address conversion circuit to convert the memory address into a relative address corresponding to allocated space for the physical-resource set and output the relative address to a random access memory (RAM); and read the variable value from the relative address of the RAM, or writing the variable value into the relative address of the RAM.

### Claim 14 (depends on 13)

The non-transitory computer program product of claim 13, wherein the operation is associated with an I/O command read from a submission queue, or is a background operation irrelevant from a host.

### Claim 15 (depends on 13)

The non-transitory computer program product of claim 13, wherein the RAM comprises a plurality of segments of temporary space and each segment of temporary space stores variables associated with a specific flash physical-resource set.

### Claim 16 (depends on 13)

The non-transitory computer program product of claim 13, comprising program code of the FLT to:
during the performance of the operation, drive a flash interface to access user data of the physical-resource set according to the variable value.

### Claim 17 (depends on 13)

The non-transitory computer program product of claim 13, wherein the address conversion circuit comprises:
the set-selection register, arranged to operably store the number corresponding to the physical-resource set;
a multiplier, coupled to the set-selection register, arranged to operably time the number corresponding to the physical-resource set by a total length of temporary space that is allocated for each physical-resource set to generate a calculation result; and
an adder, coupled to the multiplier, arranged to operably plus the calculation result to the memory address to generate the relative address and output the relative address to the RAM.

### Claim 18 (depends on 17)

The non-transitory computer program product of claim 17, wherein the address conversion circuit comprises:
an offset register, coupled to the multiplier, arranged to operably store the total length of temporary space that is allocated for each physical-resource set.

### Claim 19 (depends on 13)

The non-transitory computer program product of claim 13, wherein the address conversion circuit comprises:
the set-selection register, arranged to operably store the number associated with the physical-resource set;
a plurality of address registers, wherein each address register is arranged to operably store a start address of the RAM that is associated with a specific physical-resource set;
an adder; and
a multiplexer, coupled to the set-selection register, the address registers and the adder, arranged to operably connect one of the address registers to the adder according to a control signal corresponding to the number associated with the physical-resource set,
wherein the adder is arranged to operably plus the start address of the connected address register to the memory address to generate the relative address, and output the relative address to the RAM.

### Claim 20 (depends on 13)

The non-transitory computer program product of claim 13, wherein each physical-resource set comprises a portion of channels and a portion of Logical Unit Numbers (LUNs).