# US 2020/0401495 A1 · Message selection for hardware tracing in system-on-chip post-silicon debugging

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- Number: US 2020/0401495 A1
- Document ID: US20200401495A1
- Status: Published application
- Kind: A1
- Application number: 16/448,091
- Filed: 2019-06-21
- Published: 2020-12-24
- Earliest claimed: 2019-06-21
- Assignees: International Business Machines Corporation; The Board of Trustees of the University of Illinois
- Applicants: International Business Machines Corporation; The Board of Trustees of the University of Illinois
- Inventors: Flavio M De Paula; Debjit Pal; Shobha Vasudevan; Abhishek Sharma
- Web page: https://patentgrep.com/patent/US20200401495A1

## CPC

- G06F 11/348: {Circuit details, i.e. tracer hardware}
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06F 9/546: {Message passing systems or structures, e.g. queues}
- G06F 15/17318: {Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all}
- G06F 30/30: Circuit design
- G06F 30/3308: using simulation
- G06F 2115/08: Intellectual property [IP] blocks or IP cores
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Techniques message selection for hardware tracing in receiving system-on-chip (SoC) post-silicon debugging are described herein. An aspect includes receiving SoC design information corresponding to an SoC. Another aspect includes determining, based on the SoC design information, a set of messages that are exchanged between blocks of the SoC. Another aspect includes determining a set of possible combinations of messages of the set of messages. Another aspect includes determining a respective mutual information gain for each possible combination of messages in the set of possible combinations of messages. Another aspect includes selecting a combination of messages having a highest determined mutual information gain for monitoring via hardware tracing in the SoC.

## Claims

### Claim 1

A system comprising a processor configured to:
receive system-on-chip (SoC) design information corresponding to an SoC;
determine, based on the SoC design information, a set of messages that are exchanged between blocks of the SoC;
determine a set of possible combinations of messages of the set of messages;
determine a respective mutual information gain for each possible combination of messages in the set of possible combinations of messages; and
select a combination of messages having a highest determined mutual information gain for monitoring via hardware tracing in the SoC.

### Claim 2 (depends on 1)

The system of claim 1, wherein the SoC design information comprises a flow-based specification corresponding to a usage scenario of the SoC and a mapping of the flow-based specification to a hardware implementation of the SoC.

### Claim 3 (depends on 2)

The system of claim 2, wherein the set of messages correspond to the usage scenario.

### Claim 4 (depends on 1)

The system of claim 1, the processor configured to:
receive a hardware constraint; and
apply the hardware constraint to the set of possible combinations of messages, wherein the mutual information gain is not determined for any possible combination of messages that does not fit the hardware constraint.

### Claim 5 (depends on 4)

The system of claim 4, wherein the hardware constraint comprises a width of a trace buffer of the SoC.

### Claim 6 (depends on 4)

The system of claim 4, the processor configured to:
based on the hardware constraint, add one or more additional messages to the selected combination of messages for monitoring via hardware tracing in the SoC.

### Claim 7 (depends on 1)

The system of claim 1, the processor configured to:
update the SoC design information to include a respective trace connection corresponding to each message in the selected combination of messages.

### Claim 8

A computer-implemented method, comprising:
receiving, by a processor, system-on-chip (SoC) design information corresponding to an SoC;
determining, based on the SoC design information, a set of messages that are exchanged between blocks of the SoC;
determining a set of possible combinations of messages of the set of messages;
determining a respective mutual information gain for each possible combination of messages in the set of possible combinations of messages; and
selecting a combination of messages having a highest determined mutual information gain for monitoring via hardware tracing in the SoC.

### Claim 9 (depends on 8)

The computer-implemented method of claim 8, wherein the SoC design information comprises a flow-based specification corresponding to a usage scenario of the SoC and a mapping of the flow-based specification to a hardware implementation of the SoC.

### Claim 10 (depends on 9)

The computer-implemented method of claim 9, wherein the set of messages correspond to the usage scenario.

### Claim 11 (depends on 8)

The computer-implemented method of claim 8, comprising:
receiving a hardware constraint; and
applying the hardware constraint to the set of possible combinations of messages, wherein the mutual information gain is not determined for any possible combination of messages that does not fit the hardware constraint.

### Claim 12 (depends on 11)

The computer-implemented method of claim 11, wherein the hardware constraint comprises a width of a trace buffer of the SoC.

### Claim 13 (depends on 11)

The computer-implemented method of claim 11, comprising:
based on the hardware constraint, add one or more additional messages to the selected combination of messages for monitoring via hardware tracing in the SoC.

### Claim 14 (depends on 8)

The computer-implemented method of claim 8, comprising:
update the SoC design information to include a respective trace connection corresponding to each message in the selected combination of messages.

### Claim 15

A computer program product comprising:
a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing device to cause the processing device to perform a method comprising:
receiving system-on-chip (SoC) design information corresponding to an SoC;
determining, based on the SoC design information, a set of messages that are exchanged between blocks of the SoC;
determining a set of possible combinations of messages of the set of messages;
determining a respective mutual information gain for each possible combination of messages in the set of possible combinations of messages; and
selecting a combination of messages having a highest determined mutual information gain for monitoring via hardware tracing in the SoC.

### Claim 16 (depends on 15)

The computer program product of claim 15, wherein the SoC design information comprises a flow-based specification corresponding to a usage scenario of the SoC and a mapping of the flow-based specification to a hardware implementation of the SoC.

### Claim 17 (depends on 16)

The computer program product of claim 16, wherein the set of messages correspond to the usage scenario.

### Claim 18 (depends on 15)

The computer program product of claim 15, the method comprising:
receiving a hardware constraint; and
applying the hardware constraint to the set of possible combinations of messages, wherein the mutual information gain is not determined for any possible combination of messages that does not fit the hardware constraint.

### Claim 19 (depends on 18)

The computer program product of claim 18, wherein the hardware constraint comprises a width of a trace buffer of the SoC.

### Claim 20 (depends on 18)

The computer program product of claim 18, the method comprising:
based on the hardware constraint, add one or more additional messages to the selected combination of messages for monitoring via hardware tracing in the SoC.