# US 2020/0401490 A1 · Efficient power scheme for redundancy

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- Number: US 2020/0401490 A1
- Document ID: US20200401490A1
- Status: Published application
- Kind: A1
- Application number: 16/446,457
- Filed: 2019-06-19
- Published: 2020-12-24
- Earliest claimed: 2019-06-19
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Richard E. Fackenthal; Duane R. Mills
- Web page: https://patentgrep.com/patent/US20200401490A1

## CPC

- G06F 11/2015: {Redundant power supplies (power supply failure G06F1/30)}
- G11C 11/221: {using ferroelectric capacitors}
- G06F 11/2017: {where memory access, memory control or I/O control functionality is redundant (redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089)}
- G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)}
- G06F 11/3062: {where the monitored property is the power consumption (power management in a computing system G06F1/3203)}
- G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00)
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 7/1087: {Data input latches}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- G11C 29/83: {with reduced power consumption}
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for efficient power scheme for redundancy are described. A memory device may include circuitry that stores memory address information related to one or more defective or unreliable memory components and that compares memory address information to memory addresses targeted for memory access operations. The memory device may selectively distribute a targeted memory address to one or more circuits within the circuitry based on whether those circuits store memory address information. Additionally or alternatively, the memory device may selectively power one or more circuits within the circuitry based on whether those circuits store memory address information.

## Claims

### Claim 1

An apparatus, comprising:
a first latch configured to store an address bit associated with an access line identified as defective;
a second latch configured to store at least one bit that indicates that the first latch is storing the address bit;
a first logic component coupled with the first latch and configured to perform a logic operation on a signal representing the address bit stored at the first latch; and
a second logic component coupled with the second latch and configured to send, to the first logic component based at least in part on the at least one bit stored at the second latch, a second signal representing a second address bit associated with an access line selected for a memory access operation.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
a conductive path coupled with an output of the second latch and an input of the second logic component; and
a second conductive path coupled with an output of the second logic component and an input of the first logic component.

### Claim 3 (depends on 2)

The apparatus of claim 2, further comprising:
an inverter coupled with the output of the second logic component; and
a third conductive path coupled with an output of the inverter and a second input of the first logic component.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising:
a third logic component coupled with an output of the first logic component and an output of the second latch.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first latch is configured to output the signal representing the address bit to the first logic component and the second latch is configured to output a third signal representing the at least one bit to the second logic component.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the second logic component comprises an AND component, the apparatus further comprising: an inverter coupled with the AND component and the first logic component, the inverter configured to send a third signal representing a complemented version of the second address bit to the first logic component.

### Claim 7

A method, comprising:
storing, at a first latch, a first address bit associated with a memory component identified as unreliable;
storing, at a second latch, an enable bit that indicates the first latch is storing the at least one first address bit;
performing a logic operation on signals representing the enable bit and a second address bit that is associated with a memory component selected for a memory access operation; and
outputting a signal representing the second address bit to a logic component coupled with the first latch based at least in part on the logic operation.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
performing, at the logic component, a second logic operation on signals representing the first and second address bits; and
outputting a second signal based at least in part on the second logic operation.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
performing, at a second logic component, a third logic operation on the second signal output by the logic component and a third signal representing the enable bit; and
outputting a fourth signal indicating whether the first address bit matches the second address bit based at least in part on the third logic operation.

### Claim 10 (depends on 7)

The method of claim 7, further comprising:
receiving, at second logic component, the enable bit from the second latch; and
receiving, at the second logic component, the second address bit, wherein the second logic component performs the logic operation.

### Claim 11 (depends on 7)

The method of claim 7, further comprising:
inverting the second address bit after performing the logic operation; and
signaling the inverted second address bit to the logic component coupled with the first latch.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
performing a second logic operation on signals representing the first address bit, the second address bit, and the inverted second address bit.

### Claim 13

An apparatus, comprising:
a set of latches configured to store memory address information;
a latch configured to store at least one bit that indicates whether the set of latches stores a memory address associated with an access line identified as defective;
a power supply coupled with the set of latches and the latch; and
a switching component coupled with the latch and configured to activate or deactivate based at least in part on the at least one bit stored at the latch.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the switching component is coupled with an output of the latch and is configured to receive a signal representing the at least one bit.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein the switching component is configured to establish a conductive path from the power supply to the set of latches when the at least one bit indicates that the set of latches stores the memory address.

### Claim 16 (depends on 13)

The apparatus of claim 13, wherein the switching component is configured to isolate the power supply from the set of latches when the at least one bit indicates that the set of latches stores information different than the memory address.

### Claim 17 (depends on 13)

The apparatus of claim 13, further comprising:
a second set of latches configured to store a second memory address associated with a second access line identified as defective; and
a second latch configured to store at least one second bit that indicates whether the second set of latches stores the second memory address.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the switching component is configured to isolate the power supply from the second set of latches and the second latch when the at least one bit stored by the latch indicates that the set of latches stores information different than memory address information.

### Claim 19 (depends on 17)

The apparatus of claim 17, further comprising:
a second switching component coupled with the second latch and configured to establish a second conductive path from the power supply to the second set of latches based at least in part on the at least one second bit stored at the second latch.

### Claim 20

A method, comprising:
storing, at a set of latches, a memory address associated with a memory component identified as unreliable;
storing, at a latch, at least one bit that indicates that the set of latches is storing the memory address;
sending a signal representing the at least one bit to a switching component coupled with the set of latches and a power supply; and
activating the switching component, based at least in part on the signal representing the at least one bit, to couple the power supply with the set of latches.

### Claim 21 (depends on 20)

The method of claim 20, further comprising:
storing, at a second set of latches, a second memory address associated with a second memory component identified as unreliable, wherein activating the switching component couples the power supply with the second set of latches.

### Claim 22 (depends on 20)

The method of claim 20, further comprising:
storing, at a second latch, at least one second bit that indicates whether a second set of latches is storing a second memory address associated with a second memory component identified as unreliable; and
modifying a state of a second switching component based at least in part on the at least one second bit, the second switching component coupled with the power supply and the second set of latches.

### Claim 23 (depends on 22)

The method of claim 22, wherein modifying the state of the second switching component comprises:
deactivating the switching component, when the at least one second bit indicates that the second set of latches is storing the second memory address, to isolate the power supply from the second set of latches.

### Claim 24 (depends on 22)

The method of claim 22, wherein modifying the state of the second switching component comprises:
activating the second switching component, when the at least one second bit indicates that the second set of latches is not storing the second memory address, to establish a conductive path from the power supply to the second set of latches.