# US 2020/0401475 A1 · Detection and correction of data bit errors using error correction codes

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2020/0401475 A1
- Document ID: US20200401475A1
- Status: Published application
- Kind: A1
- Application number: 17/007,942
- Filed: 2020-08-31
- Published: 2020-12-24
- Earliest claimed: 2018-07-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Lien Linus Lu
- Web page: https://patentgrep.com/patent/US20200401475A1

## CPC

- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/102: {Error in check bits}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- H03M 13/05: using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)}
- H03M 13/3738: {with judging correct decoding}
- H03M 13/3746: {with iterative decoding}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.

## Claims

### Claim 1

A system, comprising:
an encoder circuit configured to encode data with an error correction code to form a codeword;
a memory configured to store the codeword; and
a decoder circuit comprising:
a bit error detection circuit configured to determine a presence of bit errors in the codeword;
a bit flipping circuit configured to:
flip a bit of the codeword to form a bit-flipped codeword; and
determine a location of a bit error based on the bit-flipped codeword in response to the bit errors being present in the codeword; and
a correction circuit configured to correct the codeword for the bit error based on the bit-flipped codeword.

### Claim 2 (depends on 1)

The system of claim 1, wherein the decoder circuit further comprises a syndrome generation circuit configured to generate a syndrome of the codeword.

### Claim 3 (depends on 1)

The system of claim 1, wherein the decoder circuit further comprises a syndrome generation circuit configured to generate a syndrome of the bit-flipped codeword.

### Claim 4 (depends on 1)

The system of claim 1, wherein the bit error detection circuit comprises a comparator configured to determine whether a syndrome of the codeword is equal to a value of zero.

### Claim 5 (depends on 1)

The system of claim 1, wherein the bit error detection circuit comprises a comparator configured to determine whether a syndrome of the bit-flipped codeword is equal to a column of an H-matrix generated based on the data of the codeword.

### Claim 6 (depends on 1)

The system of claim 1, wherein the bit error detection circuit comprises a comparator configured to determine the location of the bit error based on a comparison between a syndrome of the bit-flipped codeword and a column of an H-matrix generated based on the data of the codeword.

### Claim 7 (depends on 1)

The system of claim 1, wherein the bit error detection circuit comprises:
a comparator configured to compare a syndrome of the codeword to each column of an H-matrix generated based on the data of the codeword; and
a shift register configured to store an output of the comparator.

### Claim 8 (depends on 1)

The system of claim 1, wherein the bit flipping circuit comprises a logic circuit configured to flip the bit of the codeword.

### Claim 9 (depends on 1)

The system of claim 1, wherein the bit flipping circuit comprises:
a shift register with an array of bits; and
a logic circuit configured to perform an XOR operation between the codeword and the array of bits of the shift register.

### Claim 10 (depends on 1)

The system of claim 1, wherein the correction circuit is configured to:
separate data bits and error correcting code bits of the corrected codeword; and
output the data bits.

### Claim 11

A system, comprising:
an encoder circuit configured to encode data with an error correction code to form a codeword;
a memory configured to store the codeword; and
a decoder circuit comprising:
an error detection circuit configured to determine a presence of a bit error in the codeword;
a logic circuit configured to flip a bit of the codeword to determine a location of the bit error in response to the bit error being present in the codeword;
a syndrome generation circuit configured to generate a syndrome of the bit-flipped codeword; and
a correction circuit configured to correct the codeword for the bit error based on the syndrome.

### Claim 12 (depends on 11)

The system of claim 11, wherein the decoder circuit further comprises a syndrome generation circuit configured to generate a syndrome of the bit-flipped codeword.

### Claim 13 (depends on 11)

The system of claim 11, wherein the bit error detection circuit comprises a comparator configured to determine whether the syndrome of the bit-flipped codeword is equal to a value of zero.

### Claim 14 (depends on 11)

The system of claim 11, wherein the correction circuit is configured to correct the codeword for the bit error in response to the syndrome of the bit-flipped codeword not being equal to a value of zero.

### Claim 15 (depends on 11)

The system of claim 11, wherein the correction circuit is configured to output the data of the codeword in response to the syndrome of the codeword being equal to a value of zero.

### Claim 16

A method, comprising:
encoding data with an error correction code to form a codeword;
determining, using a detection circuit, whether a single bit error or a plurality of bit errors are present in the codeword;
flipping, using a logic circuit, a bit of the codeword to form a bit-flipped codeword and to determine a location of a bit error in the codeword based on the bit-flipped codeword in response to the plurality of bit errors being present in the codeword; and
correcting, using a correction circuit, the plurality of bit errors in the determined location of the codeword.

### Claim 17 (depends on 16)

The method of claim 16, wherein the determining comprises generating a syndrome of the codeword.

### Claim 18 (depends on 16)

The method of claim 16, wherein the determining comprises generating a syndrome of the bit-flipped codeword.

### Claim 19 (depends on 16)

The method of claim 16, further comprising comparing a syndrome of the codeword with a value of zero.

### Claim 20 (depends on 16)

The method of claim 16, wherein the flipping comprises performing a bitwise XOR operation on the codeword.