# US 2020/0401474 A1 · Optimized error-correcting code (ecc) for data protection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401474 A1 - Document ID: US20200401474A1 - Status: Published application - Kind: A1 - Application number: 17/008,442 - Filed: 2020-08-31 - Published: 2020-12-24 - Earliest claimed: 2017-04-28 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Alain ARTIERI; Deepti Vijayalakshmi SRIRAMAGIRI; Dexter Tamio CHUN; Jungwon SUH - Web page: https://patentgrep.com/patent/US20200401474A1 ## CPC - G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/064: {Management of blocks} - G06F 3/0673: {Single storage device} - H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes - H04L 1/0041: {Arrangements at the transmitter end} - H04L 1/0045: {Arrangements at the receiver end} - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 2029/0411: {Online error correction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M. ## Claims ### Claim 1 A method for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message, comprising: initializing a matrix M to store selected three-bit codes, wherein each row of the matrix M is associated with a row weight, and wherein the row weight of each row of the matrix M indicates a number of set bits in the row; selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M; comparing the first three-bit code with each of a plurality of error syndromes in a set D of error syndromes; and based on no comparison of the first three-bit code with each of the plurality of error syndromes in the set D of error syndromes matching a three-bit code in the matrix M, calculating new error syndromes and storing the new error syndromes in the set D of error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M. ### Claim 2 (depends on 1) The method of claim 1, further comprising: based on at least one comparison of the first three-bit code with each of the plurality of error syndromes in the set D of error syndromes matching a three-bit code in the matrix M, rejecting the first three-bit code. ### Claim 3 (depends on 1) The method of claim 1, wherein comparing the first three-bit code with each of the plurality of error syndromes in the set D of error syndromes comprises determining a bitwise exclusive OR (XOR) of the first three-bit code with each of the plurality of error syndromes in the set D of error syndromes. ### Claim 4 (depends on 1) The method of claim 1, further comprising: initializing the set L of three-bit combinations of the number of bits n of the error correcting code with all possible three-bit combinations of the number of bits n of the error correcting code. ### Claim 5 (depends on 1) The method of claim 1, further comprising: initializing the set D of error syndromes as an empty list. ### Claim 6 (depends on 1) The method of claim 1, further comprising: determining whether the matrix M has at least k columns, wherein k is a number of the plurality of bits of the message to be protected by the ECC, wherein, based on the matrix M not having at least k columns, performing the selecting the first three-bit code. ### Claim 7 (depends on 6) The method of claim 6, wherein, based on the matrix M having k columns, setting the matrix M as the parity check matrix. ### Claim 8 (depends on 1) The method of claim 1, further comprising: determining whether the set L of three-bit combinations of the number of bits n of the error correcting code is empty, wherein based on the set L of three-bit combinations of the number of bits n of the error correcting code not being empty, performing the selecting the first three-bit code. ### Claim 9 (depends on 1) The method of claim 1, further comprising: determining whether the set L of three-bit combinations of the number of bits n of the error correcting code is less than the number of the plurality of bits of the message to be protected by the ECC, wherein, based on the set L of three-bit combinations of the number of bits n of the error correcting code not being less than the number of the plurality of bits of the message to be protected by the ECC, performing the selecting the first three-bit code. ### Claim 10 (depends on 1) The method of claim 1, further comprising: generating, by a source module, a first plurality of bits representing the ECC based on the matrix M, wherein a number of the first plurality of bits representing the ECC is greater than a minimum number of bits required for single error correction and double error detection (SECDED) protection of the plurality of bits of the message to be protected by the ECC; and emitting, by the source module, the plurality of bits of the message and the first plurality of bits representing the ECC. ### Claim 11 (depends on 10) The method of claim 10, further comprising: receiving, at a destination module coupled to the source module over a high-speed data link, the plurality of bits of the message and the first plurality of bits representing the ECC; generating, by the destination module, a second plurality of bits representing the ECC, wherein a number of the second plurality of bits representing the ECC is greater than the minimum number of bits required for SECDED protection of the plurality of bits of the message; and determining, by the destination module, whether or not at least one bit of the plurality of bits of the message is corrupted based on the ECC. ### Claim 12 (depends on 11) The method of claim 11, further comprising: determining, by the destination module, whether multiple bits of the plurality of bits of the message are corrupted based on the second plurality of bits representing the ECC; and sending, by the destination module to the source module, a notification that multiple bits of the plurality of bits of the message are corrupted so that the source module can resend the plurality of bits of the message. ### Claim 13 (depends on 11) The method of claim 11, wherein the number of the first plurality of bits representing the ECC is less than or equal to a capacity of the high-speed data link over which the destination module receives the plurality of bits of the message. ### Claim 14 (depends on 11) The method of claim 11, wherein the source module comprises a System on Chip (SoC), and wherein the destination module comprises a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM) module. ### Claim 15 (depends on 11) The method of claim 11, wherein the source module comprises an LPDDR SDRAM module, and wherein the destination module comprises a SoC. ### Claim 16 (depends on 10) The method of claim 10, wherein the minimum number of bits required for the SECDED protection of the plurality of bits of the message is nine bits. ### Claim 17 (depends on 1) The method of claim 1, wherein the number of bits n of the ECC is greater than nine bits. ### Claim 18 (depends on 1) The method of claim 1, wherein the number of bits n of the ECC is 14 bits. ### Claim 19 (depends on 1) The method of claim 1, wherein the number of bits n of the ECC is 16 bits. ### Claim 20 (depends on 1) The method of claim 1, wherein each column of the matrix M is associated with a column weight, and wherein the column weight comprises a number of set bits in the column. ### Claim 21 (depends on 20) The method of claim 20, wherein the row weight of each row of the matrix M indicates an XOR input width needed to calculate a parity bit for the plurality of bits of the message. ### Claim 22 (depends on 20) The method of claim 20, wherein all column weights of the matrix M is three. ### Claim 23 (depends on 20) The method of claim 20, wherein all column weights of the matrix M are identical, wherein the identical weight indicates an AND gate input width needed to calculate each bit of an error location vector for the plurality of bits of the message. ### Claim 24 A non-transitory computer-readable medium storing computer-executable instructions for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message, the computer-executable instructions comprising: at least one instruction for initializing a matrix M to store selected three-bit codes, wherein each row of the matrix M is associated with a row weight, and wherein the row weight of each row of the matrix M indicates a number of set bits in the row; at least one instruction for selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M; at least one instruction for comparing the first three-bit code with each of a plurality of error syndromes in a set D of error syndromes; and at least one instruction for calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes in the set D of error syndromes matching a three-bit code in the matrix M, new error syndromes and storing the new error syndromes in the set D of error syndromes, wherein the new error syndromes are calculated based on a comparison of the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.