# US 2020/0401461 A1 · Providing self-resetting multi-producer multi-consumer semaphores in distributed processor-based systems

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2020/0401461 A1
- Document ID: US20200401461A1
- Status: Published application
- Kind: A1
- Application number: 16/443,954
- Filed: 2019-06-18
- Published: 2020-12-24
- Earliest claimed: 2019-06-18
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Colin Beaton Verrilli; Natarajan Vaidhyanathan
- Web page: https://patentgrep.com/patent/US20200401461A1

## CPC

- G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F 2209/522: Manager
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Providing self-resetting multi-producer multi-consumer semaphores in distributed processor-based systems is disclosed. In one aspect, a synchronization management circuit provides a semaphore including a counting semaphore value indicator, a current wait count indicator, and a target wait count indicator. When a consumer completes a wait operation, the synchronization management circuit adjusts the value of the current wait count indicator towards the value of the target wait count indicator, and compares the value of the current wait count indicator to the value of the target wait count indicator. If the value of the current wait count indicator has reached the value of the target wait count indicator, the synchronization management circuit infers that all consumers have observed the semaphore, and accordingly resets both the counting semaphore value indicator and the current wait count indicator to an initial wait value to place the semaphore in its initial state for reuse.

## Claims

### Claim 1

A distributed processor-based system, comprising:
a plurality of processor devices; and
a synchronization management circuit communicatively coupled to the plurality of processor devices and comprising a plurality of semaphores each comprising:
a counting semaphore value indicator;
a current wait count indicator; and
a target wait count indicator;
the synchronization management circuit configured to:
determine that a value of a current wait count indicator of a semaphore of the plurality of semaphores equals a value of a target wait count indicator of the semaphore; and
responsive to determining that the value of the current wait count indicator of the semaphore equals the value of the target wait count indicator of the semaphore:
reset a value of a counting semaphore value indicator of the semaphore to an initial semaphore value; and
reset the value of the current wait count indicator of the semaphore to an initial wait value.

### Claim 2 (depends on 1)

The distributed processor-based system of claim 1, wherein the synchronization management circuit is further configured to:
receive an indication that a wait operation for the semaphore of the plurality of semaphores is completed; and
responsive to receiving the indication that the wait operation for the semaphore is completed, adjust the value of the current wait count indicator of the semaphore towards the value of the target wait count indicator of the semaphore.

### Claim 3 (depends on 2)

The distributed processor-based system of claim 2, wherein:
the value of the target wait count indicator of the semaphore is a non-zero integer;
the initial wait value is zero (0); and
the synchronization management circuit is configured to adjust the value of the current wait count indicator of the semaphore towards the value of the target wait count indicator of the semaphore by incrementing the current wait count indicator of the semaphore.

### Claim 4 (depends on 2)

The distributed processor-based system of claim 2, wherein:
the value of the target wait count indicator of the semaphore is zero (0);
the initial wait value is a non-zero integer; and
the synchronization management circuit is configured to adjust the value of the current wait count indicator of the semaphore towards the value of the target wait count indicator of the semaphore by decrementing the current wait count indicator of the semaphore.

### Claim 5 (depends on 2)

The distributed processor-based system of claim 2, wherein the synchronization management circuit comprises a global synchronization management (GSM) circuit communicatively coupled to a plurality of local synchronization management (LSM) circuits corresponding to the plurality of processor devices of the distributed processor-based system.

### Claim 6 (depends on 5)

The distributed processor-based system of claim 5, wherein an LSM circuit of the plurality of LSM circuits is configured to provide, to the GSM circuit, the indication that the wait operation for the semaphore is completed.

### Claim 7 (depends on 5)

The distributed processor-based system of claim 5, wherein the GSM circuit is configured to, responsive to determining that the value of the current wait count indicator of the semaphore equals the value of the target wait count indicator of the semaphore, provide a reset indication to the plurality of LSM circuits.

### Claim 8 (depends on 1)

The distributed processor-based system of claim 1, wherein the synchronization management circuit is further configured to:
receive an indication to perform an increment operation on the value of the counting semaphore value indicator of the semaphore, wherein the indication to perform the increment operation comprises a target wait count value;
increment the counting semaphore value indicator of the semaphore responsive to receiving the indication to perform the increment operation; and
set the value of the target wait count indicator of the semaphore to the target wait count value.

### Claim 9 (depends on 1)

The distributed processor-based system of claim 1, wherein the synchronization management circuit is further configured to:
receive an indication to perform a decrement operation on the value of the counting semaphore value indicator of the semaphore, wherein the indication to perform the decrement operation comprises a target wait count value;
decrement the counting semaphore value indicator of the semaphore responsive to receiving the indication to perform the decrement operation; and
set the value of the target wait count indicator of the semaphore to the target wait count value.

### Claim 10 (depends on 1)

The distributed processor-based system of claim 1 integrated into an integrated circuit (IC).

### Claim 11 (depends on 1)

The distributed processor-based system of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile processor-based device; a wearable processor-based device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

### Claim 12

A distributed processor-based system for providing a self-resetting multi-producer multi-consumer semaphore, comprising:
a means for determining that a value of a current wait count indicator of a semaphore equals a value of a target wait count indicator of the semaphore;
a means for resetting a value of a counting semaphore value indicator of the semaphore to an initial semaphore value, responsive to determining that the value of the current wait count indicator of the semaphore equals the value of the target wait count indicator of the semaphore; and
a means for resetting the value of the current wait count indicator to an initial wait value, responsive to determining that the value of the current wait count indicator of the semaphore equals the value of the target wait count indicator of the semaphore.

### Claim 13 (depends on 12)

The distributed processor-based system of claim 12, further comprising:
a means for receiving an indication that a wait operation for the semaphore is completed; and
a means for adjusting the value of the current wait count indicator of the semaphore towards the value of the target wait count indicator of the semaphore, responsive to receiving the indication that the wait operation is completed.

### Claim 14 (depends on 13)

The distributed processor-based system of claim 13, wherein:
the value of the target wait count indicator of the semaphore is a non-zero integer;
the initial wait value is zero (0); and
the means for adjusting the value of the current wait count indicator of the semaphore towards the value of the target wait count indicator of the semaphore comprises a means for incrementing the current wait count indicator of the semaphore.

### Claim 15 (depends on 13)

The distributed processor-based system of claim 13, wherein:
the value of the target wait count indicator of the semaphore is zero (0);
the initial wait value is a non-zero integer; and
the means for adjusting the value of the current wait count indicator of the semaphore towards the value of the target wait count indicator of the semaphore comprises a means for decrementing the current wait count indicator of the semaphore.

### Claim 16 (depends on 12)

The distributed processor-based system of claim 12, further comprising:
a means for receiving an indication to perform an increment operation on the value of the counting semaphore value indicator of the semaphore, wherein the indication to perform the increment operation comprises a target wait count value;
a means for incrementing the counting semaphore value indicator of the semaphore responsive to receiving the indication to perform the increment operation; and
a means for setting the value of the target wait count indicator of the semaphore to the target wait count value.

### Claim 17 (depends on 12)

The distributed processor-based system of claim 12, further comprising:
a means for receiving an indication to perform a decrement operation on the value of the counting semaphore value indicator of the semaphore, wherein the indication to perform the decrement operation comprises a target wait count value;
a means for decrementing the counting semaphore value indicator of the semaphore responsive to receiving the indication to perform the decrement operation; and
a means for setting the value of the target wait count indicator of the semaphore to the target wait count value.

### Claim 18

A method for providing a self-resetting multi-producer multi-consumer semaphore, comprising:
determining, by a synchronization management circuit of a distributed processor-based system, that a value of a current wait count indicator of a semaphore equals a value of a target wait count indicator of the semaphore; and
responsive to determining that the value of the current wait count indicator of the semaphore equals the value of the target wait count indicator of the semaphore:
resetting a value of a counting semaphore value indicator of the semaphore to an initial semaphore value; and
resetting the value of the current wait count indicator to an initial wait value.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
receiving an indication that a wait operation for the semaphore is completed; and
responsive to receiving the indication that the wait operation for the semaphore is completed, adjusting the value of the current wait count indicator of the semaphore towards the value of the target wait count indicator of the semaphore.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
the value of the target wait count indicator of the semaphore is a non-zero integer;
the initial wait value is zero (0); and
adjusting the value of the current wait count indicator of the semaphore towards the value of the target wait count indicator of the semaphore comprises incrementing the current wait count indicator of the semaphore.

### Claim 21 (depends on 19)

The method of claim 19, wherein:
the value of the target wait count indicator of the semaphore is zero (0);
the initial wait value is a non-zero integer; and
adjusting the value of the current wait count indicator of the semaphore towards the value of the target wait count indicator of the semaphore comprises decrementing the current wait count indicator of the semaphore.

### Claim 22 (depends on 19)

The method of claim 19, wherein the synchronization management circuit comprises a global synchronization management (GSM) circuit communicatively coupled to a plurality of local synchronization management (LSM) circuits of the distributed processor-based system.

### Claim 23 (depends on 22)

The method of claim 22, further comprising providing, by an LSM circuit of the plurality of LSM circuits, the indication that the wait operation for the semaphore is completed to the GSM circuit.

### Claim 24 (depends on 22)

The method of claim 22, further comprising, responsive to determining that the value of the current wait count indicator of the semaphore equals the value of the target wait count indicator of the semaphore, providing, by the GSM circuit, a reset indication to the plurality of LSM circuits.

### Claim 25 (depends on 18)

The method of claim 18, further comprising:
receiving, by the synchronization management circuit, an indication to perform an increment operation on the value of the counting semaphore value indicator of the semaphore, wherein the indication to perform the increment operation comprises a target wait count value;
incrementing the counting semaphore value indicator of the semaphore responsive to receiving the indication to perform the increment operation; and
setting the value of the target wait count indicator of the semaphore to the target wait count value.

### Claim 26 (depends on 18)

The method of claim 18, further comprising:
receiving, by the synchronization management circuit, an indication to perform a decrement operation on the value of the counting semaphore value indicator of the semaphore, wherein the indication to perform the decrement operation comprises a target wait count value;
decrementing the counting semaphore value indicator of the semaphore responsive to receiving the indication to perform the decrement operation; and
setting the value of the target wait count indicator of the semaphore to the target wait count value.

### Claim 27

A computer program product stored on a non-transitory computer-readable storage medium and including instructions that, when executed by a processor device, cause the processor device to:
determine that a value of a current wait count indicator of a semaphore equals a value of a target wait count indicator of the semaphore; and
responsive to determining that the value of the current wait count indicator of the semaphore equals the value of the target wait count indicator of the semaphore:
reset a value of a counting semaphore value indicator of the semaphore to an initial semaphore value; and
reset the value of the current wait count indicator to an initial wait value.

### Claim 28 (depends on 27)

The computer program product of claim 27, wherein the instructions further cause the processor device to:
receive an indication that a wait operation for the semaphore is completed; and
responsive to receiving the indication that the wait operation for the semaphore is completed, increment the value of the current wait count indicator of the semaphore.

### Claim 29 (depends on 27)

The computer program product of claim 27, wherein the instructions further cause the processor device to:
receive an indication to perform an increment operation on the value of the counting semaphore value indicator of the semaphore, wherein the indication to perform the increment operation comprises a target wait count value;
increment the counting semaphore value indicator of the semaphore responsive to receiving the indication to perform the increment operation; and
set the value of the target wait count indicator of the semaphore to the target wait count value.

### Claim 30 (depends on 27)

The computer program product of claim 27, wherein the instructions further cause the processor device to:
receive an indication to perform a decrement operation on the value of the counting semaphore value indicator of the semaphore, wherein the indication to perform the decrement operation comprises a target wait count value;
decrement the counting semaphore value indicator of the semaphore responsive to receiving the indication to perform the decrement operation; and
set the value of the target wait count indicator of the semaphore to the target wait count value.