# US 2020/0401442 A1 · Information processor, method for controlling information processor, and non-transitory computer-readable storage medium for storing control program for information processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401442 A1 - Document ID: US20200401442A1 - Status: Published application - Kind: A1 - Application number: 16/892,340 - Filed: 2020-06-04 - Published: 2020-12-24 - Earliest claimed: 2019-06-20 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Go Endo - Web page: https://patentgrep.com/patent/US20200401442A1 ## CPC - G06F 9/4818: {Priority circuits therefor} - G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An information processing apparatus includes: a control circuit; an interface circuit; and an information processing circuit, wherein the control circuit is configured to: execute a first processing that includes causing the information processing circuit to individually execute a plurality of divided first control commands as one processing unit in a predetermined execution order, via the interface circuit; execute an interrupt detection processing that includes detecting an interrupt issued from the information processing circuit or the interface circuit; execute a command generation processing that includes generating a second control command for identifying an interrupt factor of the interrupt detected by the interrupt detection processing; and execute a processing order change processing that includes preferentially arranging the second control command generated by the command generation processing over the unexecuted first control commands to change the execution order. ## Claims ### Claim 1 An information processing apparatus comprising: a control circuit; an interface circuit; and an information processing circuit, wherein the control circuit is configured to: execute a first processing that includes causing the information processing circuit to individually execute a plurality of divided first control commands as one processing unit in a predetermined execution order, via the interface circuit; execute an interrupt detection processing that includes detecting an interrupt issued from the information processing circuit or the interface circuit; execute a command generation processing that includes generating a second control command for identifying an interrupt factor of the interrupt detected by the interrupt detection processing; and execute a processing order change processing that includes preferentially arranging the second control command generated by the command generation processing over the unexecuted first control commands to change the execution order. ### Claim 2 (depends on 1) The information processing apparatus according to claim 1, wherein the interrupt detection processing is configured to determine priority of the detected interrupt, select the interrupt based on the priority, and cause the command generation processing to generate the second control command. ### Claim 3 (depends on 1) The information processing apparatus according to claim 1, wherein the interface circuit includes a first control circuit and a second control circuit, the first and second control circuit being configured to execute the control command, and in executing the first control commands and the second control command in the execution order, the processing circuit is configured to cause the first control circuit to execute the control commands at execution of the first control commands, stop the operation of the first control circuit, cause the second control circuit to perform processing at execution of the second control command, and restart the operation of the first control circuit to execute the first control commands at completion of the execution of the second control command. ### Claim 4 (depends on 1) The information processing apparatus according to claim 1, wherein the control circuit is further configured to execute a registration processing that includes acquiring a unified command including the plurality of first control commands, and registering all of the first control commands included in the unified command as the one processing unit in the execution order, in a storage area, wherein the first processing is configured to individually acquire the plurality of first control commands registered as one processing unit in the storage area in the execution order, and cause the information processing circuit to sequentially execute the first control commands via the interface circuit. ### Claim 5 A control method for an information processing apparatus including a control device, an interface device, and an arithmetic processing device, wherein the control device is configured to: cause the arithmetic processing device to individually execute a plurality of divided first control commands as one processing unit in a predetermined execution order, via the interface device; detect an interrupt issued from the arithmetic processing device or the interface device; generate a second control command for identifying an interrupt factor of the detected interrupt; preferentially arrange the generated second control command over the unexecuted first control commands to change the execution order; and execute the first control commands and the second control command in the changed execution order. ### Claim 6 A non-transitory computer-readable storage medium for storing a control program which causes an information processor to perform processing, the information processor including a control device, an interface device, and an arithmetic processing device, the processing comprising: causing the arithmetic processing device to individually execute a plurality of divided first control commands as one processing unit in a predetermined execution order, via the interface device; detecting an interrupt issued from the arithmetic processing device or the interface device; generating a second control command for identifying an interrupt factor of the detected interrupt; preferentially arranging the generated second control command over the unexecuted first control commands to change the execution order; and executing the first control commands and the second control command in the changed execution order.