# US 2020/0401414 A1 · Multiplier-Accumulator Circuitry and Pipeline using Floating Point Data, and Methods of using Same

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- Number: US 2020/0401414 A1
- Document ID: US20200401414A1
- Status: Published application
- Kind: A1
- Application number: 16/900,319
- Filed: 2020-06-12
- Published: 2020-12-24
- Earliest claimed: 2019-06-21
- Assignees: Flex Logix Technologies, Inc.
- Applicants: Flex Logix Technologies, Inc.
- Inventors: Frederick A. Ware; Cheng C. Wang; Fang-Li Yuan; Nitish U. Natu
- Web page: https://patentgrep.com/patent/US20200401414A1

## CPC

- G06F 9/3893: {controlled in tandem, e.g. multiplier-accumulator}
- G06F 7/501: Half or full adders, i.e. basic adder cells for one denomination
- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G06F 9/30014: {with variable precision}
- G06F 9/30079: {Pipeline control instructions, e.g. multicycle NOP}
- G06F 15/17375: {One dimensional, e.g. linear array, ring}
- G06F 30/323: Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
- G06F 2207/3884: Pipelining
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An integrated circuit including a multiplier-accumulator execution pipeline including a plurality of multiplier-accumulator circuits to, in operation, perform multiply and accumulate operations, wherein each multiplier-accumulator circuit includes: (i) a multiplier to multiply first input data, having a first floating point data format, by a filter weight data, having the first floating point data format, and generate and output a product data having a second floating point data format, and (ii) an accumulator, coupled to the multiplier of the associated MAC circuit, to add second input data and the product data output by the associated multiplier to generate sum data. The plurality of multiplier-accumulator circuits of the multiplier-accumulator execution pipeline may be connected in series and, in operation, perform a plurality of concatenated multiply and accumulate operations.

## Claims

### Claim 1

An integrated circuit comprising:
a multiplier-accumulator execution pipeline, including a plurality of multiplier-accumulator circuits to, in operation, perform multiply and accumulate operations, wherein each multiplier-accumulator circuit includes:
a multiplier to multiply first input data, having a first floating point data format, by a filter weight data, having the first floating point data format, and to generate and output product data having a second floating point data format, and
an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second input data and the product data output by the associated multiplier to generate sum data; and
wherein, the plurality of multiplier-accumulator circuits of the multiplier-accumulator execution pipeline are connected in series and, in operation, perform a plurality of concatenated multiply and accumulate operations.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 wherein:
the first floating point data format is a floating point having a first precision and the second floating point data format is a floating point having a second precision.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 wherein:
the accumulator of each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits adds the second input data and the product data in the second floating point data format.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 wherein:
the sum data includes the second floating point data format.

### Claim 5 (depends on 1)

The integrated circuit of claim 1 further including:
first conversion circuitry, coupled to the plurality of multiplier-accumulator circuits of the multiply-accumulator execution pipeline, to convert filter weight data having a first format to the filter weight data having the first floating point data format, and
a memory, coupled the first conversion circuitry, to store the filter weight data having the first format.

### Claim 6 (depends on 1)

The integrated circuit of claim 1 wherein:
first conversion circuitry, coupled to the plurality of multiplier-accumulator circuits of the multiply-accumulator execution pipeline, to convert first input data having a first format to the first input data having the first floating point data format.

### Claim 7 (depends on 1)

The integrated circuit of claim 1 wherein:
the first conversion circuitry includes an adder.

### Claim 8 (depends on 1)

The integrated circuit of claim 1 wherein:
(i) the first floating point data format is 16 bit and the second floating point format is 24 or 32 bit or (ii) the first floating point data format is 16 bit or 24 bit and the second floating point format is 32 bit.

### Claim 9

An integrated circuit comprising:
a multiplier-accumulator execution pipeline, coupled to first memory, including a plurality of multiplier-accumulator circuits to, in operation, perform multiply and accumulate operations, wherein each multiplier-accumulator circuit includes:
a multiplier, coupled to the first memory, to multiply first input data, having a first floating point data format, by filter weight data, having the first floating point data format, and to generate and output product data having a second floating point data format, and
an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second input data and the product data output by the associated multiplier to generate sum data; and
wherein, the plurality of multiplier-accumulator circuits of the multiplier-accumulator execution pipeline are connected in series to form a ring architecture and, in operation, perform a plurality of concatenated multiply and accumulate operations.

### Claim 10 (depends on 9)

The integrated circuit of claim 9 wherein:
each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits of the multiplier-accumulator execution pipeline is connected to two multiplier-accumulator circuits of the plurality of multiplier-accumulator circuits including:
a connected first multiplier-accumulator circuit to receive the second input data therefrom, and
a connected second multiplier-accumulator circuit to output the sum data thereto.

### Claim 11 (depends on 10)

The integrated circuit of claim 10 wherein:
the second input data is the sum data output by the accumulator of the connected first multiplier-accumulator circuit.

### Claim 12 (depends on 11)

The integrated circuit of claim 11 wherein:
the first floating point data format is a floating point having a first precision and the second floating point data format is a floating point having a second precision.

### Claim 13 (depends on 11)

The integrated circuit of claim 11 wherein:
the accumulator of each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits adds the second input data and the product data in the second floating point data format.

### Claim 14 (depends on 11)

The integrated circuit of claim 11 wherein:
the sum data includes the second floating point data format.

### Claim 15

An integrated circuit comprising:
first memory to store data;
first conversion circuitry, coupled to the first memory, to receive and convert the data from the first memory to first input data having a first floating point data format;
second memory to store filter weight data having a second data format;
second conversion circuitry, coupled to the second memory, to receive and convert the filter weight data from the second memory to filter weight data format having the first floating point data format;
a multiplier-accumulator execution pipeline, coupled to the first conversion circuitry and the second conversion circuitry, wherein the multiplier-accumulator execution pipeline includes a plurality of multiplier-accumulator circuits to, in operation, perform multiply and accumulate operations, wherein each multiplier-accumulator circuit includes:
a multiplier, coupled to the first memory, to multiply the first input data, having the first floating point data format, by the filter weight data, having the first floating point data format, and to generate and output product data having a second floating point data format, and
an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second input data and the product data output by the associated multiplier to generate sum data; and
wherein, the plurality of multiplier-accumulator circuits of the multiplier-accumulator execution pipeline are connected in series to form a ring architecture and, in operation, perform a plurality of concatenated multiply and accumulate operations.

### Claim 16 (depends on 15)

The integrated circuit of claim 15 wherein:
each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits is connected to two multiplier-accumulator circuits of the plurality of multiplier-accumulator circuits including:
a connected first multiplier-accumulator circuit to receive the second input data therefrom, and
a connected second multiplier-accumulator circuit to output the sum data thereto.

### Claim 17 (depends on 16)

The integrated circuit of claim 16 wherein:
the second input data is the sum data output by the accumulator of the connected first multiplier-accumulator circuit.

### Claim 18 (depends on 17)

The integrated circuit of claim 17 wherein:
the first floating point data format is a floating point having a first precision and the second floating point data format is a floating point having a second precision.

### Claim 19 (depends on 15)

The integrated circuit of claim 15 wherein:
the sum data includes the second floating point data format, and
the first floating point data format is a floating point having a first precision and the second floating point data format is a floating point having a second precision.

### Claim 20 (depends on 19)

The integrated circuit of claim 19 wherein:
the first floating point data format is 16 bit and the second floating point format is 24 bit or 32 bit.

### Claim 21 (depends on 19)

The integrated circuit of claim 19 wherein:
the first conversion circuitry and the second conversion circuitry each includes an adder.