# US 2020/0401413 A1 · Reduced precision based programmable and simd dataflow architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401413 A1 - Document ID: US20200401413A1 - Status: Published application - Kind: A1 - Application number: 16/447,588 - Filed: 2019-06-20 - Published: 2020-12-24 - Earliest claimed: 2019-06-20 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Kailash GOPALAKRISHNAN; Sunil SHUKLA; Jungwook CHOI; Silvia MUELLER; Bruce FLEISCHER; Vijayalakshmi SRINIVASAN; Ankur AGRAWAL; Jinwook OH - Web page: https://patentgrep.com/patent/US20200401413A1 ## CPC - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/30014: {with variable precision} - G06F 9/3814: {Implementation provisions of instruction buffers, e.g. prefetch buffer; banks} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Various embodiments are provided for using a reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture in a computing environment. One or more instructions between a plurality of execution units (EUs) operating in parallel within each one of a plurality of execution elements (EEs). ## Claims ### Claim 1 A method for implementing a reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture in a computing environment by a processor, comprising: executing, in lock step, one or more instructions between a plurality of execution units (EUs) operating in parallel within each one of a plurality of execution elements (EEs). ### Claim 2 (depends on 1) The method of claim 1, further including exchanging data via one or more connections between each one of the plurality of EEs, wherein each of the plurality of EEs include an instruction buffer and supports an instruction-set-architecture (ISA). ### Claim 3 (depends on 1) The method of claim 1, further including facilitating a data exchange by one or more register files shared between the plurality of EEs or using one or more first-in-first-out connections, wherein the one or more FIFIO connections carry one or more data values in parallel. ### Claim 4 (depends on 1) The method of claim 1, further including executing, in lock step, the one or more instructions by each of the plurality of EUs while operating on different data elements, wherein each of the plurality of EUs are in lock step with each other in the same one of the plurality of EEs. ### Claim 5 (depends on 1) The method of claim 1, further including performing a reduced precision operation by one or more of the plurality of EEs according to operands and types of the one or more instructions. ### Claim 6 (depends on 1) The method of claim 1, further including performing a higher precision operation by one or more of the plurality of EEs according to one or more operands and types of the one or more instructions, wherein the one or more of the plurality of EEs performing the higher precision operation are special functional units (SFUs). ### Claim 7 (depends on 1) The method of claim 1, further including: loading and storing one or more data values on a memory medium by one or more of the plurality of EEs; sending the one or more data values from one of the plurality of EEs to an alternative one of the plurality of EEs; or receiving the one or more data values by one of the plurality of EEs from an alternative one of the plurality of EEs. ### Claim 8 A system for implementing a reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture in a computing environment, comprising: one or more computers with executable instructions that when executed cause the system to: execute, in lock step, one or more instructions between a plurality of execution units (EUs) operating in parallel within each one of a plurality of execution elements (EEs). ### Claim 9 (depends on 8) The system of claim 8, wherein the executable instructions exchange data via one or more connections between each one of the plurality of EEs, wherein each of the plurality of EEs include an instruction buffer and supports an instruction-set-architecture (ISA). ### Claim 10 (depends on 8) The system of claim 8, wherein the executable instructions facilitate a data exchange by one or more register files shared between the plurality of EEs or using one or more first-in-first-out connections, wherein the one or more FIFIO connections carry one or more data values in parallel. ### Claim 11 (depends on 8) The system of claim 8, wherein the executable instructions execute, in lock step, the one or more instructions by each of the plurality of EUs while operating on different data elements, wherein each of the plurality of EUs are in lock step with each other in the same one of the plurality of EEs. ### Claim 12 (depends on 8) The system of claim 8, wherein the executable instructions perform a reduced precision operation by one or more of the plurality of EEs according to operands and types of the one or more instructions. ### Claim 13 (depends on 8) The system of claim 8, wherein the executable instructions perform a higher precision operation by one or more of the plurality of EEs according to one or more operands and types of the one or more instructions, wherein the one or more of the plurality of EEs performing the higher precision operation are special functional units (SFUs). ### Claim 14 (depends on 8) The system of claim 8, wherein the executable instructions: load and store one or more data values on a memory medium by one or more of the plurality of EEs; send the one or more data values from one of the plurality of EEs to an alternative one of the plurality of EEs; or receive the one or more data values by one of the plurality of EEs from an alternative one of the plurality of EEs. ### Claim 15 A computer program product for implementing a reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture by a processor in a computing environment, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising: an executable portion that executes, in lock step, one or more instructions between a plurality of execution units (EUs) operating in parallel within each one of a plurality of execution elements (EEs). ### Claim 16 (depends on 15) The computer program product of claim 15, further including an executable portion that exchanges data via one or more connections between each one of the plurality of EEs, wherein each of the plurality of EEs include an instruction buffer and supports an instruction-set-architecture (ISA). ### Claim 17 (depends on 15) The computer program product of claim 15, further including an executable portion that facilitates a data exchange by one or more register files shared between the plurality of EEs or using one or more first-in-first-out connections, wherein the one or more FIFIO connections carry one or more data values in parallel. ### Claim 18 (depends on 15) The computer program product of claim 15, further including an executable portion that executes, in lock step, the one or more instructions by each of the plurality of EUs while operating on different data elements, wherein each of the plurality of EUs are in lock step with each other in the same one of the plurality of EEs. ### Claim 19 (depends on 15) The computer program product of claim 15, further including an executable portion that: performs a reduced precision operation by one or more of the plurality of EEs according to operands and types of the one or more instructions; or performs a higher precision operation by one or more of the plurality of EEs according to one or more operands and types of the one or more instructions, wherein the one or more of the plurality of EEs performing the higher precision operation are special functional units (SFUs). ### Claim 20 (depends on 15) The computer program product of claim 15, further including an executable portion that: loads and stores one or more data values on a memory medium by one or more of the plurality of EEs; sends the one or more data values from one of the plurality of EEs to an alternative one of the plurality of EEs; or receives the one or more data values by one of the plurality of EEs from an alternative one of the plurality of EEs.