# US 2020/0401412 A1 · Hardware support for dual-memory atomic operations

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- Number: US 2020/0401412 A1
- Document ID: US20200401412A1
- Status: Published application
- Kind: A1
- Application number: 16/450,300
- Filed: 2019-06-24
- Published: 2020-12-24
- Earliest claimed: 2019-06-24
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Robert PAWLOWSKI; Joshua B. FRYMAN; Vincent CAVE; Eric M. SCHWARTZ; Ivan B. GANEV; Jason M. HOWARD; Ankit MORE; Shaden SMITH
- Web page: https://patentgrep.com/patent/US20200401412A1

## CPC

- G06F 9/30087: {Synchronisation or serialisation instructions}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/3834: {Maintaining memory consistency}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3853: {of compound instructions}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Disclosed embodiments relate to hardware support for dual-memory atomic operations. In one example, a processor includes multiple cores, each including multiple multi-threaded pipelines (MTPs), each associated with a memory, an atomic unit (ATMU) to perform atomic operations and a write-combine buffer (WCB) to manage access to and locks of cache lines in the associated memory, each MTP including fetch and decode stages to fetch and decode an instruction having fields to specify first and second memory locations and an opcode calling for a first MTP to send a request to a second MTP of the multiple MTPs, the second MTP being associated with a memory to which the first memory location is mapped, and to perform an atomic dual-memory operation on the first and second memory locations using its associated ATMU and WCB to perform the request.

## Claims

### Claim 1

A processor comprising a plurality of cores, each core comprising:
a plurality of multi-threaded pipelines (MTPs), each associated with a memory, an atomic unit (ATMU) to perform atomic operations and a write-combine buffer (WCB) to manage access to and locks of cache lines in the associated memory, each of the MTPs comprising:
a fetch stage to fetch an instruction;
a decode stage to decode the instruction having fields to specify an opcode and first and second memory locations, the opcode calling for a first MTP of the plurality of MTPs to send a request to a second MTP of the plurality of MTPs, the second MTP to perform an atomic dual-memory operation on the first and second memory locations, the second MTP associated with a memory to which the first memory location is mapped; and
an execution stage to execute the instruction as per the opcode;
wherein the second MTP is to perform the request using its associated ATMU and WCB.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the dual-memory operation comprises a read-read, wherein a third register is used to calculate a first memory address from which to read a value into a first register, and to calculate a second memory address from which to read a value into a second register.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the dual-memory operation comprises a read-write, wherein a third register is used to calculate a first memory address from which to read a value into a first register, and to calculate a second memory address to which to write a value stored in a second register.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the dual-memory operation comprises a write-write, wherein a third register is used to calculate a first memory address to which to write a value stored in a first register, and to calculate a second memory address to which to write a value stored in a second register.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the first and second memory locations are addressed by first and second memory addresses, and wherein the instruction further specifies an immediate used in calculating the second memory address.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the dual memory operation comprises an atomic exchange (XC) on the first of the first and second memory locations, while one of five different operations is executed on the second of the first and second memory locations, the five different operations comprising read (R), write (W), atomic add (XA), atomic increment (XI), and an atomic exchange (XC).

### Claim 7 (depends on 1)

The processor of claim 1, wherein the first and second memory locations are within a single cache line.

### Claim 8 (depends on 1)

The processor of claim 1, wherein the first MTP is to route the instruction to an ATMU coupled to a memory in which the dual memory locations are located.

### Claim 9 (depends on 1)

The processor of claim 1, wherein the instruction further specifies a size for each of the first and second memory locations.

### Claim 10 (depends on 1)

The processor of claim 1, wherein each of the cores comprises four MTPs each processing sixteen threads in parallel, two single-threaded pipelines (STPs), two one-megabyte scratchpad memories (SPMs), and one 2 GB in-package memory (IPM).

### Claim 11

A method performed by a processor comprising a plurality of cores each comprising a plurality of multi-threaded pipelines (MTPs), each MTP associated with a memory, an atomic unit (ATMU) to perform atomic operations and a write-combine buffer (WCB) to manage access to and locks of cache lines in its associated memory; the method comprising:
initializing the processor;
fetching an instruction by a first MTP of the plurality of MTPs;
decoding the instruction by the first MTP, the instruction having fields to specify an opcode and first and second memory locations, the opcode calling for the first MTP to send a request to a second MTP of the plurality of MTPs, the second MTP to perform an atomic dual-memory operation on the first and second memory locations, the second MTP being associated with a memory to which the first memory location is mapped;
executing the instruction, by the first MTP, to send the request to the second MTP; and
executing the request, by the second MTP, using its associated ATMU and WCB.

### Claim 12 (depends on 11)

The method of claim 11, wherein the dual-memory operation comprises a read-read, wherein a third register is used to calculate a first memory address from which to read a value into a first register, and to calculate a second memory address from which to read a value into a second register.

### Claim 13 (depends on 11)

The method of claim 11, wherein the dual-memory operation comprises a read-write, wherein a third register is used to calculate a first memory address from which to read a value into a first register, and to calculate a second memory address to which to write a value stored in a second register.

### Claim 14 (depends on 11)

The method of claim 11, wherein the dual-memory operation comprises a write-write, wherein a third register is used to calculate a first memory address to which to write a value stored in a first register, and to calculate a second memory address to which to write a value stored in a second register.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first and second memory locations are addressed by first and second memory addresses, and wherein the instruction further specifies an immediate used in calculating the second memory address.

### Claim 16 (depends on 11)

The method of claim 11, wherein the dual memory operation comprises an atomic exchange (XC) on the first of the first and second memory locations, while one of five different operations is executed on the second of the first and second memory locations; the five different operations comprising read (R), write (W), atomic add (XA), atomic increment (XI), and an atomic exchange (XC).

### Claim 17 (depends on 11)

The method of claim 11, wherein the first and second memory locations are within a single cache line.

### Claim 18 (depends on 11)

The method of claim 11, wherein the first MTP is to route the instruction to an ATMU coupled to a memory in which the dual memory locations are located.

### Claim 19 (depends on 11)

The method of claim 11, wherein the instruction further specifies a size for each of the first and second memory locations.

### Claim 20 (depends on 11)

The method of claim 11, wherein each of the cores comprises four MTPs each processing sixteen threads in parallel, two single-threaded pipelines (STPs), two one-megabyte scratchpad memories (SPMs), and one 2 GB in-package memory (IPM).