# US 2020/0401411 A1 · Flow Control for Multi-threaded Access to Contentious Resource(s) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401411 A1 - Document ID: US20200401411A1 - Status: Published application - Kind: A1 - Application number: 16/565,752 - Filed: 2019-09-10 - Published: 2020-12-24 - Earliest claimed: 2019-06-24 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Stanislav A OKS; Wonseok KIM - Web page: https://patentgrep.com/patent/US20200401411A1 ## CPC - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/526: {Mutual exclusion algorithms} - G06F 9/3009: {Thread control instructions} - G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/5016: {the resource being the memory} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Described herein is a system and method of performing flow control for multi-threaded access to contentious resource(s) (e.g., shared memory). A request to enter a critical section of code by a particular thread of a plurality of concurrent threads is received. A determination is made as to whether or not to allow the particular thread to enter the critical section of code based, at least in part, upon a CPU core associated with the particular thread, a state associated with the particular thread, and/or a processing rate in the critical session of code associated with the particular thread. When it is determined to allow the particular thread to enter the critical section of code, the particular thread is allowed to enter the critical section of code. ## Claims ### Claim 1 A system for flow control, comprising: a processing system comprising a processor and a memory having computer-executable instructions stored thereupon which, when executed by the processor, cause the processing system to: receive a request to enter a critical section of code by a particular thread of a plurality of concurrent threads; determine whether or not to allow the particular thread to enter the critical section of code based, at least in part, upon a CPU core associated with the particular thread; and when it is determined to allow the particular thread to enter the critical section of code, allow the particular thread to enter the critical section of code. ### Claim 2 (depends on 1) The system of claim 1, wherein the determination of whether or not to allow the particular thread to enter the critical section of code is further based, at least in part, upon a state associated with the particular thread. ### Claim 3 (depends on 1) The system of claim 1, wherein the determination of whether or not to allow the particular thread to enter the critical section of code is further based, at least in part, upon a processing rate in the critical session of code associated with the particular thread. ### Claim 4 (depends on 1) The system of claim 1, wherein the determination of whether or not to allow the particular thread to enter the critical section of code is further based, at least in part, upon a policy to allow only one thread per each CPU core to enter the critical section of code. ### Claim 5 (depends on 1) The system of claim 1, wherein the critical section of code comprises a request to access a shared database resource. ### Claim 6 (depends on 5) The system of claim 5, wherein the shared database resource comprises a page of an index. ### Claim 7 (depends on 1) The system of claim 1, wherein the critical section of code comprises a request to access a shared memory. ### Claim 8 (depends on 1) The system of claim 1, wherein the CPU core is one of a plurality of CPU cores of a multi-core processor chip. ### Claim 9 (depends on 1) The system of claim 1, wherein the CPU core is one of a plurality of CPU cores, at least some of the plurality of CPU cores on different processor chips. ### Claim 10 A method of performing flow control for multi-threaded access to a contentious resource, comprising: receiving a request to enter a critical section of code by a particular thread of a plurality of concurrent threads; determining whether or not to allow the particular thread to enter the critical section of code based, at least in part, upon a state associated with the particular thread; and when it is determined to allow the particular thread to enter the critical section of code, allowing the particular thread to enter the critical section of code. ### Claim 11 (depends on 10) The method of claim 10, wherein the determination of whether or not to allow the particular thread to enter the critical section of code is further based, at least in part, upon a CPU core associated with the particular thread. ### Claim 12 (depends on 11) The method of claim 11, wherein the determination of whether or not to allow the particular thread to enter the critical section of code is further based, at least in part, upon a policy to allow only one thread per each CPU core to enter the critical section of code. ### Claim 13 (depends on 10) The method of claim 10, wherein the determination of whether or not to allow the particular thread to enter the critical section of code is further based, at least in part, upon a processing rate of in the critical session of code associated with the particular thread. ### Claim 14 (depends on 10) The method of claim 10, wherein the critical section of code comprises a request to access a shared database resource. ### Claim 15 (depends on 14) The method of claim 14, wherein the shared database resource comprises a page of an index. ### Claim 16 (depends on 10) The method of claim 10, wherein the critical section of code comprises a request to access a shared memory. ### Claim 17 A computer storage media storing computer-readable instructions that when executed cause a computing device to: receive a request to enter a critical section of code by a particular thread of a plurality of concurrent threads; determine whether or not to allow the particular thread to enter the critical section of code based, at least in part, upon a CPU core associated with the particular thread associated with the particular thread, a state associated with the particular thread, and a processing rate in the critical session of code; and when it is determined to allow the particular thread to enter the critical section of code, allow the particular thread to enter the critical section of code. ### Claim 18 (depends on 17) The computer storage media of claim 17, wherein the determination of whether or not to allow the particular thread to enter the critical section of code is further based, at least in part, upon a policy to allow only one thread per each CPU core to enter the critical section of code. ### Claim 19 (depends on 17) The computer storage media of claim 17, wherein the critical section of code comprises a request to access a shared database resource. ### Claim 20 (depends on 17) The computer storage media of claim 17, wherein the critical section of code comprises a request to access a shared memory.