# US 2020/0401407 A1 · Microcontroller with Configurable Logic Peripheral > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401407 A1 - Document ID: US20200401407A1 - Status: Published application - Kind: A1 - Application number: 16/568,058 - Filed: 2019-09-11 - Published: 2020-12-24 - Earliest claimed: 2019-06-20 - Assignees: Microchip Technology Incorporated - Applicants: Microchip Technology Incorporated - Inventors: Ryan Foss - Web page: https://patentgrep.com/patent/US20200401407A1 ## CPC - G06F 9/30101: {Special purpose registers} - G06F 15/7867: {with reconfigurable architecture} - G06F 9/30029: {Logical and Boolean instructions, e.g. XOR, NOT} - G06F 13/287: {Multiplexed DMA (G06F13/30 takes precedence)} - G11C 8/10: Decoders - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A microcontroller has a central processing unit, memory, I/O ports and a plurality of peripheral units, wherein one of the peripheral units is a configurable logic cell. The configurable logic cell is formed by a look-up table formed by a plurality of memory cells receiving a predefined number of input address signals selectable from internal signals provided by the peripheral units and at least one external signal provided by at least one external pin and generating an output signal. The central processing unit is configured to directly provide input address signals for the look-up table. ## Claims ### Claim 1 A microcontroller comprising a central processing unit, memory, I/O ports and a plurality of peripheral units, wherein one of the peripheral units is a configurable logic cell, wherein the configurable logic cell is formed by a look-up table formed by a plurality of memory cells receiving a predefined number of input address signals selectable from internal signals provided by the peripheral units and at least one external signal provided by at least one external pin and generating an output signal and wherein the central processing unit is configured to directly provide input address signals for the look-up table. ### Claim 2 (depends on 1) The microcontroller according to claim 1, wherein the configurable logic cell comprises an input multiplexer circuit configured to select the predefined number of input address signals from said internal signals and the at least one external signal and further comprises a special function input register coupled between outputs of the input multiplexer circuit and an address input of the look-up table, wherein the special function input register receives and buffers the selected input signals and wherein the central processing unit is configured to read from and write to the special function input register. ### Claim 3 (depends on 2) The microcontroller according to claim 2, wherein the special function register is memory mapped to a data memory. ### Claim 4 (depends on 1) The microcontroller according to claim 1, wherein the configurable logic cell comprises an input multiplexer circuit configured to select the predefined number of input signals from said internal signals and the at least one external signal and further comprises a special function input register coupled with inputs of the input multiplexer circuit wherein the central processing unit is configured to read from and write to the special function input register to directly provide input signals to the look-up table. ### Claim 5 (depends on 4) The microcontroller according to claim 4, wherein the special function register is memory mapped to a data memory. ### Claim 6 (depends on 2) The microcontroller according to claim 2, wherein the configurable logic cell comprises an input multiplexer circuit configured to select the predefined number of input signals from said internal signals and the at least one external signal and further comprises a further special function input register coupled with inputs of the input multiplexer circuit wherein the central processing unit is configured to read from and write to the further special function input register to directly provide input signals to the look-up table. ### Claim 7 (depends on 6) The microcontroller according to claim 6, wherein the further special function register is memory mapped to a data memory. ### Claim 8 (depends on 1) The microcontroller according to claim 1, wherein the look-up table comprises a plurality of 1-bit memory cells. ### Claim 9 (depends on 8) The microcontroller according to claim 8, wherein the plurality of 1-bit memory cells are memory-mapped to the data memory. ### Claim 10 (depends on 8) The microcontroller according to claim 8, wherein the plurality of 1-bit memory cells are memory-mapped to the program memory. ### Claim 11 (depends on 10) The microcontroller according to claim 10, wherein the program memory is flash memory. ### Claim 12 (depends on 8) The microcontroller according to claim 8, further comprising a direct memory access controller configurable to transfer data into the plurality of 1-bit memory cells. ### Claim 13 (depends on 8) The microcontroller according to claim 8, further comprising a multiplexer having a plurality of inputs coupled with the plurality of 1-bit memory cells, wherein the multiplexer is controlled to select an output of one of the memory cells corresponding to said input address signals. ### Claim 14 (depends on 8) The microcontroller according to claim 8, further comprising an address decoder configured to select one of the memory cells corresponding to input address signals received at the address decoder. ### Claim 15 (depends on 1) The microcontroller according to claim 1, further comprising a logic circuit being coupled with an output of the look-up table. ### Claim 16 (depends on 15) The microcontroller according to claim 15, wherein the logic circuit comprises a mode multiplexer having a first input coupled with the output of the look-up table, a second input coupled with an output of a first flip-flop, wherein a data input of the first flip flop is coupled with the output of the look-up table and a clock input of the flip-flop is coupled with a clock input of the logic circuit, wherein the mode multiplexer is controlled by a mode register. ### Claim 17 (depends on 16) The microcontroller according to claim 16, wherein the multiplexer comprises a third input coupled with an output of an AND gate, the AND gate having a first input coupled with the clock input and a second input coupled with an output of a second flip-flop, wherein a data input of the second flip-flop is coupled with output of the look-up table and a clock input of the second flip-flop is coupled with an output of an XOR gate, wherein a first input of the XOR gate is coupled with the clock input and a second input of the XOR gate is coupled with the output of the second flip-flop. ### Claim 18 A method of operating a microcontroller comprising a central processing unit, memory, I/O ports and a plurality of peripheral units, wherein one of the peripheral units is a configurable logic cell, wherein the configurable logic cell is formed by a look-up table formed by a plurality of memory cells receiving a predefined number of input address signals and generating an output signal and wherein the central processing unit is configured to directly provide input address signals for the look-up table, the method comprising: configuring the look-up table by loading predefined data into memory cells of the look-up table; selecting address signals from internal signals provided by the peripheral units and external signals provided by at least one external pin; buffering the selected address signals in a register or latch. ### Claim 19 (depends on 18) The method according to claim 18, further comprising overwriting the register or latch by the central processing unit under program control. ### Claim 20 (depends on 18) The method according to claim 18, wherein configuring the look-up table is performed by transferring data into the memory cells by the central processing unit or a DMA controller. ### Claim 21 (depends on 18) The method according to claim 18, wherein configuring the look-up table is performed by memory-mapping the memory cells to a flash memory and by programming the microcontroller.