# US 2020/0401406 A1 · Streaming engine with stream metadata saving for context switching

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- Number: US 2020/0401406 A1
- Document ID: US20200401406A1
- Status: Published application
- Kind: A1
- Application number: 17/011,808
- Filed: 2020-09-03
- Published: 2020-12-24
- Earliest claimed: 2013-07-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Joseph Zbiciak; Timothy D. Anderson
- Web page: https://patentgrep.com/patent/US20200401406A1

## CPC

- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30014: {with variable precision}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/30098: {Register arrangements}
- G06F 9/30112: {comprising data of variable length}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/32: Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence)
- G06F 9/34: Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)}
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)}
- G06F 9/3867: {using instruction pipelines}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 13/14: Handling requests for interconnection or transfer
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 2212/452: Instruction code
- G06F 2212/60: Details of cache memory
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

## Claims

### Claim 1

A data processing apparatus comprising:
a processing core;
a memory;
a register file; and
a data processing engine configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, the data processing engine including:
an address generator to generate addresses corresponding to locations in the memory;
a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses; and
an output to supply the data elements received from the memory to the processing core as the data stream, and wherein the data processing engine is configured to, in response to an interrupt of the data stream:
copy metadata of the data stream into at least one register of the register file;
discard a memory request that has not been processed by the data processing engine when the interrupt is processed;
discard a portion of the plurality of data elements stored in the buffer; and
mark a portion of the memory storing the plurality of data elements as invalid.

### Claim 2 (depends on 1)

The data processing apparatus of claim 1, wherein:
the metadata of the data stream includes a current address, the current address being generated by the address generator and corresponding to a next data element to fetched from the memory.

### Claim 3 (depends on 2)

The data processing apparatus of claim 2, wherein:
the data stream includes a plurality of loops, each loop having a total iteration count representing a number of times the loop is to repeat, and wherein the metadata of the data stream additionally includes information indicating remaining iterations for each of the loops.

### Claim 4 (depends on 1)

The data processing apparatus of claim 1, wherein:
the data stream is inactive.

### Claim 5 (depends on 1)

The data processing apparatus of claim 1, wherein:
the portion of the memory associated with the data stream marked as invalid includes a plurality of slots.

### Claim 6 (depends on 5)

The data processing apparatus of claim 5, wherein:
each of the plurality of slots is 64 bytes.

### Claim 7 (depends on 5)

The data processing apparatus of claim 5, wherein:
the portion of the memory associated with the data stream marked as invalid is available for allocation and reuse.

### Claim 8 (depends on 1)

The data processing apparatus of claim 1, further comprising:
in response to a stream restore instruction, the data processing engine is configured to recall the metadata of the data stream from the at least one register of the register file.

### Claim 9 (depends on 8)

The data processing apparatus of claim 8, wherein:
in response to the stream restore instruction, the data processing engine is configured to resume providing the data stream based on the metadata of the data stream.

### Claim 10 (depends on 8)

The data processing apparatus of claim 8, wherein:
the stream restore instruction includes:
a stream number;
a segment number; and
a base register number.

### Claim 11 (depends on 10)

The data processing apparatus of claim 10, wherein:
the segment number includes one of segment 0, segment 1, segment 2, or segment 3.

### Claim 12 (depends on 11)

The data processing apparatus of claim 11, wherein:
segment 0 includes a stream template for the data stream.

### Claim 13 (depends on 11)

The data processing apparatus of claim 11, wherein:
segment 1 includes a number of remaining iterations for a plurality of loops, each loop having a total iteration count representing a number of times the loop is to repeat.

### Claim 14 (depends on 13)

The data processing apparatus of claim 13, wherein:
segment 2 includes a plurality of addresses corresponding to the plurality of loops.

### Claim 15 (depends on 13)

The data processing apparatus of claim 13, wherein:
the plurality of loops includes six loops.

### Claim 16 (depends on 1)

The data processing apparatus of claim 1, further comprising:
an interrupt handler configured to execute a stream save instruction.

### Claim 17

A method comprising:
receiving, by a data processing engine, a plurality of data elements stored in a memory;
providing, by the data processing engine, the plurality of data elements as a data stream to a processing core;
receiving, by the data processing engine, an interrupt to the data stream;
in response to the interrupt, storing, by the data processing engine, metadata of the data stream into at least one register of a register file;
discarding, by the data processing engine, memory requests that have not been processed by the data processing engine when the interrupt is received;
discarding, by the data processing engine, a portion of the data elements stored in a buffer; and
marking, by the data processing engine, a portion of the memory storing the plurality of data elements as invalid.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the metadata includes a current address, the current address being generated by an address generator and corresponding to a next data element to be fetched from the memory;
the data stream includes a plurality of loops, each loop having a total iteration count representing a number of times the loop is to repeat; and
the metadata additionally includes information indicating remaining iterations for each of the loops.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
receiving, by the data processing engine, a stream restore instruction to recall the metadata of the data stream from the at least one register of the register file; and
in response to the stream restore instruction, recalling, by the data processing engine, the metadata of the data stream from the at least one register of the register file.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
the stream restore instruction includes:
a stream number;
a segment number; and
a base register number.