# US 2020/0401403 A1 · Method and apparatus to process sha-2 secure hashing algorithm

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2020/0401403 A1
- Document ID: US20200401403A1
- Status: Published application
- Kind: A1
- Application number: 16/903,542
- Filed: 2020-06-17
- Published: 2020-12-24
- Earliest claimed: 2013-06-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kirk S. YAP; Gilbert M. WOLRICH; James D. GUILFORD; Vinodh GOPAL; Erdinc OZTURK; Sean M. GULLEY; Wajdi K. FEGHALI; Martin G. DIXON
- Web page: https://patentgrep.com/patent/US20200401403A1

## CPC

- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/30007: {to perform operations on data operands}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30098: {Register arrangements}
- G06F 9/30156: {Special purpose encoding of instructions, e.g. Gray coding}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/384: {Register renaming}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 13/4068: {Electrical coupling}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors}
- G06F 21/602: {Providing cryptographic facilities or services}
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC}
- H04L 9/3239: {involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD}
- G06F 2212/452: Instruction code
- G06F 2212/68: Details of translation look-aside buffer [TLB]
- G06F 2213/0026: PCI express
- H04L 2209/122: Hardware reduction or efficient architectures
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

## Claims

### Claim 1

A processor, comprising:
an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants; and
an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the first operand specifies a first register having at least 256 bits to store SHA-2 state variables used to perform SHA-256 round operations.

### Claim 3 (depends on 2)

The processor of claim 2, wherein the second operand specifies a second register or a memory location having at least 64 bits to store at least two messages and round constants for the SHA-256 round operations.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the first operand specifies a first register having at least 512 bits to store SHA-2 state variables used to perform SHA-512 round operations.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the instruction decoder receives a second instruction, and wherein in response to the second instruction, the execution unit is configured to perform a first part of message scheduling operations based on a plurality of first previous messages specified by the second instruction and to generate an intermediate result.

### Claim 6 (depends on 5)

The processor of claim 5, wherein the second instruction includes a third operand, a fourth operand, and a fifth operand, wherein for a current iteration i of SHA-2 round operations, the third operand specifies a location to store messages w(i−13), w(i−14), w(i−15), and w(i−16), wherein the fourth operand specifies a location to store messages w(i−9), w(i−10), w(i−11), and w(i−12), and wherein the intermediate result is stored in a location specified by the fifth operand.

### Claim 7 (depends on 6)

The processor of claim 6, wherein the intermediate result comprises w(i−3)+s0(w(i−12)), w(i−14)+s0(w(i−13)), w(i−15)+s0(w(i−14)), w(i−16)+s0(w(i−15)), and wherein function s0(x) is represented by s0(x)=(x ROTR 7) XOR (x ROTR 18) XOR (x ROTR 3).

### Claim 8 (depends on 5)

The processor of claim 5, wherein the instruction decoder receives a third instruction, and wherein in response to the third instruction, the execution unit is configured to perform a second part of the message scheduling operations on second previous messages and the intermediate result specified in the third instruction and to generate next input messages for one or more rounds operations of the SHA-2 algorithm to be performed during a next iteration of one or more rounds of SHA-2 algorithm.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the third instruction includes a sixth operand, a seventh operand, and an eighth operand, wherein for a current iteration i of SHA-2 round operations, the sixth operand specifies a register to store message w(i−5), w(i−6), w(i−7), and w(i−8), wherein the seventh operand specifies a register to store messages w(i−1), w(i−2), w(i−3), and w(i−4), and wherein the next input messages comprise w(i), w (i+1), w(i+2), and w(i+3) to be stored in a register specified by the eighth operand.

### Claim 10

A method, comprising:
receiving, at an instruction decoder, a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants; and
performing, by an execution unit coupled to the instruction decoder, one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first operand specifies a first register having at least 256 bits to store SHA-2 state variables used to perform SHA-256 round operations.

### Claim 12 (depends on 11)

The method of claim 11, wherein the second operand specifies a second register or a memory location having at least 64 bits to store at least two messages and round constants for the SHA-256 round operations.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first operand specifies a first register having at least 512 bits to store SHA-2 state variables used to perform SHA-512 round operations.

### Claim 14 (depends on 10)

The method of claim 10, wherein the instruction decoder receives a second instruction, and wherein in response to the second instruction, the execution unit is configured to perform a first part of message scheduling operations based on a plurality of first previous messages specified by the second instruction and to generate an intermediate result.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second instruction includes a third operand, a fourth operand, and a fifth operand, wherein for a current iteration i of SHA-2 round operations, the third operand specifies a location to store messages w(i−13), w(i−14), w(i−15), and w(i−16), wherein the fourth operand specifies a location to store messages w(i−9), w(i−10), w(i−11), and w(i−12), and wherein the intermediate result is stored in a location specified by the fifth operand.

### Claim 16 (depends on 15)

The method of claim 15, wherein the intermediate result comprises w(i−3)+s0(w(i−12)), w(i−14)+s0(w(i−13)), w(i−15)+s0(w(i−14)), w(i−16)+s0(w(i−15)), and wherein function s0(x) is represented by s0(x)=(x ROTR 7) XOR (x ROTR 18) XOR (x ROTR 3).

### Claim 17 (depends on 14)

The method of claim 14, wherein the instruction decoder receives a third instruction, and wherein in response to the third instruction, the execution unit is configured to perform a second part of the message scheduling operations on second previous messages and the intermediate result specified in the third instruction and to generate next input messages for one or more rounds operations of the SHA-2 algorithm to be performed during a next iteration of one or more rounds of SHA-2 algorithm.

### Claim 18 (depends on 17)

The method of claim 17, wherein the third instruction includes a sixth operand, a seventh operand, and an eighth operand, wherein for a current iteration i of SHA-2 round operations, the sixth operand specifies a register to store message w(i−5), w(i−6), w(i−7), and w(i−8), wherein the seventh operand specifies a register to store messages w(i−1), w(i−2), w(i−3), and w(i−4), and wherein the next input messages comprise w(i), w (i+1), w(i+2), and w(i+3) to be stored in a register specified by the eighth operand.

### Claim 19 (depends on 10, 11, 12, 13, 14, 15, 16, 17, 18)

A data processing system, comprising:
an interconnect;
a processor coupled the interconnect to perform a method of any of claims 10-18; and
a dynamic random access memory (DRAM) coupled to the interconnect.