# US 2020/0401352 A1 · Memory module and computing device containing the memory module

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- Number: US 2020/0401352 A1
- Document ID: US20200401352A1
- Status: Published application
- Kind: A1
- Application number: 16/906,876
- Filed: 2020-06-19
- Published: 2020-12-24
- Earliest claimed: 2019-06-20
- Assignees: AI Plus, Inc.
- Applicants: AI Plus, Inc.
- Inventors: JOHN MICHAEL SMOLKA; Carlos Rene Weissenberg
- Web page: https://patentgrep.com/patent/US20200401352A1

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 13/1668: {Details of memory controller}
- G06F 13/1694: {Configuration of memory controller to different memory types}
- G06F 13/4243: {with synchronous protocol}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the Processor to communicate with the one or more DRAMs via a memory interface.

## Claims

### Claim 1

A memory module, comprising:
one or more dynamic random-access memories (DRAMs); and
a processor configured to select a Central Processing Unit (CPU) or the Processor to communicate with the one or more DRAMs via a memory interface.

### Claim 2 (depends on 1)

The memory module of claim 1, wherein the interface is a double data rate 4 (DDR4) interface or double data rate 5 (DDR5) interface.

### Claim 3 (depends on 1)

The memory module of claim 1, wherein each of the CPU and the processor has master memory interface and the DRAM has a slave memory interface, and the master memory interface and the slave memory interface communicate via the memory interface.

### Claim 4 (depends on 1)

The memory module of claim 1, wherein the memory module has a local mode and a host mode.

### Claim 5 (depends on 4)

The memory module of claim 4, wherein in the local mode, the processor writes or reads from the DRMAs.

### Claim 6 (depends on 4)

The memory module of claim 4, wherein in the host mode, the CPU writes or reads from the DRAMs.

### Claim 7 (depends on 4)

The memory module of claim 4, further comprising one or more multiplexers for switching the memory module between the local mode and host mode.

### Claim 8 (depends on 7)

The memory module of claim 7, wherein the processor is configured to control states of the multiplexers

### Claim 9 (depends on 7)

The memory module of claim 7, wherein the multiplexers includes a first multiplexer for switching command, control, and address (CCA) signals and a second multiplexer for controlling access to the DRAM.

### Claim 10 (depends on 1)

The memory module of claim 1, further comprising a storage flash that has a storage capacity of less than 1 TB or greater than or equal to 1 TB.

### Claim 11 (depends on 1)

The memory module of claim 1, further comprising a storage flash that has a storage capacity of 1 to 4 TB or more.

### Claim 12 (depends on 1)

The memory module of claim 1, wherein the memory module is used as a persistent memory module.

### Claim 13 (depends on 1)

The memory module of claim 1, wherein the processor is a Field Programmable Gate Array (FPGA).

### Claim 14 (depends on 13)

The memory module of claim 13, wherein the FPGA performs graphics processing unit (GPU) or co-processing functions.

### Claim 15 (depends on 13)

The memory module of claim 13, wherein the FPGA is a master to communicate with the CPU.

### Claim 16 (depends on 13)

The memory module of claim 13, wherein the FPGA is configured to infer data of a file when the CPU sends the file to the memory module.

### Claim 17 (depends on 15)

The memory module of claim 15, wherein the FPGA includes Artificial Intelligence (AI) inferencing algorithms or models to perform AI inferencing.

### Claim 18 (depends on 1)

The memory module of claim 1, wherein the memory module is a dual in-line memory module (DIMM).

### Claim 19

A computing device, comprising:
one or more memory modules, each memory module comprising:
one or more dynamic random-access memories (DRAMs); and
a processor configured to select a central Processing Unit (CPU) or the Processor to communicate with the one or more DRAMs by via one or more memory interfaces.

### Claim 20

A method of reading or writing data to a memory module, comprising:
setting, by a processor of the memory module, the memory module to a local mode and one or more dynamic random-access memories (DRAMs) of the memory module to an idle mode; and
reading or writing data, by the processor, from the one or more dynamic random-access memories (DRAMs) of the memory module, via one or more memory interfaces.