# US 2020/0401347 A1 · Memory system, memory controller, and semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401347 A1 - Document ID: US20200401347A1 - Status: Published application - Kind: A1 - Application number: 16/804,037 - Filed: 2020-02-28 - Published: 2020-12-24 - Earliest claimed: 2019-06-19 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hiroshi MAEJIMA - Web page: https://patentgrep.com/patent/US20200401347A1 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06N 3/0499: Feedforward networks - G06N 3/08: Learning methods - G06N 3/09: Supervised learning - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 11/54: using elements simulating biological cells, e.g. neuron - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - G11C 2211/5644: Multilevel memory comprising counting devices - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract According to one embodiment, a memory system includes a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller. ## Claims ### Claim 1 A memory system comprising: a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the nonvolatile semiconductor memory includes a first latch circuit and a second latch circuit, and is further configured to store the arithmetic operation target data in the first latch circuit and store the weight data read from the address in the second latch circuit, and thereby perform the arithmetic operation. ### Claim 3 (depends on 2) The memory system according to claim 2, wherein the nonvolatile semiconductor memory further includes a column decoder, and is further configured to select the second latch circuit based on the address. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein the nonvolatile semiconductor memory includes a memory cell array including a plurality of memory cells, and is further configured to identify the arithmetic operation target data by way of a neural network stored in the memory cell array when the arithmetic operation target data is input. ### Claim 5 (depends on 1) The memory system according to claim 1, wherein the nonvolatile semiconductor memory is further configured to output, to the memory controller, result data indicating a degree of matching between the arithmetic operation target data and a label associated with the arithmetic operation target data. ### Claim 6 (depends on 1) The memory system according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory. ### Claim 7 (depends on 1) The memory system according to claim 1, wherein the memory controller includes a first interface circuit configured to receive arithmetic operation target data from an external apparatus and a second interface circuit configured to transmit the arithmetic operation target data to the nonvolatile semiconductor memory. ### Claim 8 A nonvolatile semiconductor memory configured to: receive, from a memory controller, a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; read the weight data from the memory cell designated by the address; perform an arithmetic operation based on the arithmetic operation target data and the weight data; and send arithmetic operation result data to the memory controller. ### Claim 9 (depends on 8) The nonvolatile semiconductor memory according to claim 8, comprising: a first latch circuit and a second latch circuit, and further configured to store the arithmetic operation target data in the first latch circuit and store the weight data read from the address in the second latch circuit, and thereby perform the arithmetic operation. ### Claim 10 (depends on 9) The nonvolatile semiconductor memory according to claim 9, further comprising: a column decoder, and further configured to select the second latch circuit based on the address. ### Claim 11 (depends on 8) The nonvolatile semiconductor memory according to claim 8, further comprising: a memory cell array including a plurality of memory cells, and further configured to identify the arithmetic operation target data by way of a neural network stored in the memory cell array when the arithmetic operation target data is input. ### Claim 12 (depends on 8) The nonvolatile semiconductor memory according to claim 8, further configured to output, to the memory controller, result data indicating a degree of matching between the arithmetic operation target data and a label associated with the arithmetic operation target data. ### Claim 13 (depends on 8) The nonvolatile semiconductor memory according to claim 8, wherein the nonvolatile semiconductor memory is a NAND flash memory. ### Claim 14 A memory controller configured to: send, to a nonvolatile semiconductor memory, a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; cause the nonvolatile semiconductor memory to perform an arithmetic operation using the arithmetic operation target data and the weight data; and receive the arithmetic operation target data from the nonvolatile semiconductor memory. ### Claim 15 (depends on 14) The memory controller according to claim 14, comprising: a first interface circuit configured to receive arithmetic operation target data from an external apparatus; and a second interface circuit configured to send the arithmetic operation target data to the nonvolatile semiconductor memory.