# US 2020/0401342 A1 · Device of Memory Modules > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401342 A1 - Document ID: US20200401342A1 - Status: Published application - Kind: A1 - Application number: 16/448,557 - Filed: 2019-06-21 - Published: 2020-12-24 - Earliest claimed: 2019-06-21 - Assignees: Eorex Corporation - Applicants: Eorex Corporation - Inventors: Cheng-Lung Lin; Wan-Tung Liang - Web page: https://patentgrep.com/patent/US20200401342A1 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0673: {Single storage device} - G06F 13/4068: {Electrical coupling} - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - H05K 1/181: associated with surface mounted components - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - H05K 2201/10022: Non-printed resistor - H05K 2201/10159: Memory - H05K 2201/10287: Metal wires as connectors or conductors - H05K 2201/10522: Adjacent components - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A memory device is provided. The device comprises a substrate, a controller, at least a tap, a plurality of memory modules, and at least two resistors. The controller connects to the substrate. The tap, the memory modules, and the resistors are set on the substrate. The tap comprises an input terminal connecting to the controller; a first output terminal; and a second output terminal. After connecting to each other in series, the memory modules connect to the first output terminal and the second output terminal. Each of the resistors connects to one of the memory modules which connect to the first output terminal and the second output terminal. Thus, command signals, address signals, and timing signals are separately sent to the memory modules through the first output terminal and the second output terminal of the tap simultaneously to process instruction or read information by the controller. ## Claims ### Claim 1 A device of memory modules, comprising at least a substrate; a controller, wherein said controller connects to said substrate to read and control command signals, address signals, and timing signals; at least a tap, wherein said tap is disposed on said substrate and connects to said controller; said tap comprises an input terminal connecting to the controller; a first output terminal; and a second output terminal; and said tap receives said command signals, address signals, and timing signals of said controller from said input terminal and separately sends out said command signals, address signals, and timing signals through said first output terminal and said second output terminal simultaneously; a plurality of memory modules, wherein said memory modules are separately disposed on said substrate; after a number of a part of said memory modules are separately connected in series with address wires and control wires, one in said part of said memory modules connects to said first output terminal; after a number of the other part of said memory modules are separately connected in series with address wires and control wires, another one in the other part of said memory modules connects to said second output terminal; and said memory modules store required instruction and information and separately send said command signals, address signals, and timing signals to said memory modules through said first output terminal and said second output terminal of said tap simultaneously to process instruction and read information by said controller; and at least two resistors, wherein said resistors are separately disposed on said substrate; one of said resistors connects to said one of said memory modules which connects to said first output terminal; another one of said resistors connects to said another one of said memory modules which connects to said second output terminal; and said resistors separately absorb reflected signals of said memory modules. ### Claim 2 (depends on 1) The device according to claim 1, wherein said controller is a central processing unit. ### Claim 3 (depends on 2) The device according to claim 2, wherein ones of said memory modules which connect to said first output terminal are disposed at a side of said substrate and the number of said ones of said memory modules is at least 4; and another ones of said memory modules which connect to said second output terminal are disposed at another side of said substrate and the number of said another ones of said memory modules is at least 4. ### Claim 4 (depends on 1) The device according to claim 1, wherein a path with which said controller processes instruction and reads information from said memory modules through said first output terminal and said second output terminal of said tap has a width of 80 millimeters. ### Claim 5 (depends on 1) The device according to claim 1, wherein each of said resistors connects to a terminal voltage. ### Claim 6 (depends on 1) The device according to claim 1, wherein at least 4 of said memory modules are grouped into a set and a plurality of said sets are disposed on said substrate in a top-down arrangement. ### Claim 7 (depends on 1) The device according to claim 1, wherein a plurality of said substrates are separately disposed with at least 4 memory modules; said memory modules on each one of said substrates have a square-matrix arrangement and connect to each other with Ω-shaped wires; and said substrates are stacked.