# US 2020/0401322 A1 · Valid data merging method, memory control circuit unit and memory storage apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401322 A1 - Document ID: US20200401322A1 - Status: Published application - Kind: A1 - Application number: 16/527,064 - Filed: 2019-07-31 - Published: 2020-12-24 - Earliest claimed: 2019-06-24 - Assignees: Phison Electronics Corp. - Applicants: Phison Electronics Corp. - Inventors: Chih-Kang Yeh - Web page: https://patentgrep.com/patent/US20200401322A1 ## CPC - G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]} - G06F 7/32: Merging, i.e. combining data contained in ordered sequence on at least two record carriers to produce a single carrier or set of carriers having all the original data in the ordered sequence {merging methods in general}(G06F7/36 takes precedence) - G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 7/14: Merging, i.e. combining at least two sets of record carriers each arranged in the same ordered sequence to produce a single set having the same ordered sequence - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A valid data merging method, a memory control circuit unit, and a memory storage device are provided. The method includes: obtaining a first system parameter corresponding to a first region and a second system parameter corresponding to a second region; determining whether the first system parameter is greater than the second system parameter; selecting a third physical erasing unit from the second region preferentially and performing a valid data merging operation by using the third physical erasing unit when the first system parameter is greater than the second system parameter; and selecting a fourth physical erasing unit from the first region preferentially and performing the valid data merging operation by using the fourth physical erasing unit when the first system parameter is not greater than the second system parameter. ## Claims ### Claim 1 A valid data merging method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erasing units, the plurality of physical erasing units are grouped into at least a first area and a second area, the first area includes a plurality of first physical erasing units of the plurality of physical erasing units and the second area includes a plurality of second physical erasing units of the plurality of physical erasing units, and the valid data merging method comprises: obtaining a first system parameter corresponding to the first area and a second system parameter corresponding to the second area when performing a valid data merging operation; determining whether the first system parameter is greater than the second system parameter; when the first system parameter is greater than the second system parameter, preferentially selecting a third physical erasing unit from the plurality of second physical erasing units of the second area, and performing the valid data merging operation by using the third physical erasing unit; and when the first system parameter is not greater than the second system parameter, preferentially selecting a fourth physical erasing unit from the plurality of first physical erasing units of the first area, and performing the valid data merging operation by using the fourth physical erasing unit. ### Claim 2 (depends on 1) The valid data merging method according to claim 1, wherein each of the plurality of first physical erasing units is programmed only by using a single page programming mode, and each of the plurality of second physical erasing units is programmed only by using a multi-page programming mode. ### Claim 3 (depends on 1) The valid data merging method according to claim 1, wherein the step of performing the valid data merging operation by using the third physical erasing unit comprises: copying at least one valid data from at least one fifth physical erasing unit, writing the at least one valid data into the third physical erasing unit by using a multi-page programming mode, and performing an erasing operation to the at least one fifth physical erasing unit, wherein the step of performing the valid data merging operation by using the fourth physical erasing unit comprises: copying the at least one valid data from the at least one fifth physical erasing unit, writing the at least one valid data into the fourth physical erasing unit by using a single page programming mode, and performing the erasing operation to the at least one fifth physical erasing unit. ### Claim 4 (depends on 3) The valid data merging method according to claim 3, wherein the plurality of physical erasing units are at least grouped into a storage area and a spare area, the third physical erasing unit and the fourth physical erasing unit belongs to the spare area, and the fifth physical erasing unit belongs to the storage area. ### Claim 5 (depends on 1) The valid data merging method according to claim 1, wherein the first system parameter and the second system parameter comprise at least one of a wear level value and a write amplification factor. ### Claim 6 A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the memory control circuit unit comprises: a host interface, configured to couple to a host system; a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erasing units, the plurality of physical erasing units are grouped into at least a first area and a second area, the first area includes a plurality of first physical erasing units of the plurality of physical erasing units and the second area includes a plurality of second physical erasing units of the plurality of physical erasing units; and a memory management circuit, coupled to the host interface and the memory interface, wherein the memory management circuit is configured to obtain a first system parameter corresponding to the first area and a second system parameter corresponding to the second area when performing a valid data merging operation, wherein the memory management circuit is further configured to determine whether the first system parameter is greater than the second system parameter, when the first system parameter is greater than the second system parameter, the memory management circuit is further configured to preferentially select a third physical erasing unit from the plurality of second physical erasing units of the second area, and perform the valid data merging operation by using the third physical erasing unit, when the first system parameter is not greater than the second system parameter, the memory management circuit is further configured to preferentially select a fourth physical erasing unit from the plurality of first physical erasing units of the first area, and perform the valid data merging operation by using the fourth physical erasing unit. ### Claim 7 (depends on 6) The memory control circuit unit according to claim 6, wherein each of the plurality of first physical erasing units is programmed only by using a single page programming mode, and each of the plurality of second physical erasing units is programmed only by using a multi-page programming mode. ### Claim 8 (depends on 6) The memory control circuit unit according to claim 6, wherein in the operation of performing the valid data merging operation by using the third physical erasing unit, the memory management circuit is further configured to copy at least one valid data from at least one fifth physical erasing unit, write the at least one valid data into the third physical erasing unit by using a multi-page programming mode, and perform an erasing operation to the at least one fifth physical erasing unit, wherein in the operation of performing the valid data merging operation by using the fourth physical erasing unit, the memory management circuit is further configured to copy the at least one valid data from the at least one fifth physical erasing unit, write the at least one valid data into the fourth physical erasing unit by using a single page programming mode, and perform the erasing operation to the at least one fifth physical erasing unit. ### Claim 9 (depends on 8) The memory control circuit unit according to claim 8, wherein the plurality of physical erasing units are at least grouped into a storage area and a spare area, the third physical erasing unit and the fourth physical erasing unit belongs to the spare area, and the fifth physical erasing unit belongs to the storage area. ### Claim 10 (depends on 6) The memory control circuit unit according to claim 6, wherein the first system parameter and the second system parameter comprise at least one of a wear level value and a write amplification factor. ### Claim 11 A memory storage apparatus, comprising: a connection interface unit, configured to couple to a host system; a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erasing units, the plurality of physical erasing units are grouped into at least a first area and a second area, the first area includes a plurality of first physical erasing units of the plurality of physical erasing units and the second area includes a plurality of second physical erasing units of the plurality of physical erasing units; and a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to obtain a first system parameter corresponding to the first area and a second system parameter corresponding to the second area when performing a valid data merging operation, wherein the memory control circuit unit is further configured to determine whether the first system parameter is greater than the second system parameter, when the first system parameter is greater than the second system parameter, the memory control circuit unit is further configured to preferentially select a third physical erasing unit from the plurality of second physical erasing units of the second area, and perform the valid data merging operation by using the third physical erasing unit, when the first system parameter is not greater than the second system parameter, the memory control circuit unit is further configured to preferentially select a fourth physical erasing unit from the plurality of first physical erasing units of the first area, and perform the valid data merging operation by using the fourth physical erasing unit. ### Claim 12 (depends on 11) The memory storage apparatus according to claim 11, wherein each of the plurality of first physical erasing units is programmed only by using a single page programming mode, and each of the plurality of second physical erasing units is programmed only by using a multi-page programming mode. ### Claim 13 (depends on 11) The memory storage apparatus according to claim 11, wherein in the operation of performing the valid data merging operation by using the third physical erasing unit, the memory control circuit unit is further configured to copy at least one valid data from at least one fifth physical erasing unit, write the at least one valid data into the third physical erasing unit by using a multi-page programming mode, and perform an erasing operation to the at least one fifth physical erasing unit, wherein in the operation of performing the valid data merging operation by using the fourth physical erasing unit, the memory control circuit unit is further configured to copy the at least one valid data from the at least one fifth physical erasing unit, write the at least one valid data into the fourth physical erasing unit by using a single page programming mode, and perform the erasing operation to the at least one fifth physical erasing unit. ### Claim 14 (depends on 13) The memory storage apparatus according to claim 13, wherein the plurality of physical erasing units are at least grouped into a storage area and a spare area, the third physical erasing unit and the fourth physical erasing unit belongs to the spare area, and the fifth physical erasing unit belongs to the storage area. ### Claim 15 (depends on 11) The memory storage apparatus according to claim 11, wherein the first system parameter and the second system parameter comprise at least one of a wear level value and a write amplification factor.