# US 2020/0401208 A1 · Dynamically changing data access bandwidth by selectively enabling and disabling data links

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- Number: US 2020/0401208 A1
- Document ID: US20200401208A1
- Status: Published application
- Kind: A1
- Application number: 16/921,159
- Filed: 2020-07-06
- Published: 2020-12-24
- Earliest claimed: 2011-07-12
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. WARE
- Web page: https://patentgrep.com/patent/US20200401208A1

## CPC

- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 1/3253: {Power saving in bus}
- G06F 1/3278: {Power saving in modem or I/O interface}
- G06F 1/3293: by switching to a less power-consuming processor, e.g. sub-CPU
- G06F 13/1694: {Configuration of memory controller to different memory types}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

An integrated circuit, comprising:
a data interface to communicate data with a memory device using a plurality of data interface circuits; and,
a control interface to transmit control packets to the memory device using a plurality of control driver circuits, the control packets including an indicator of a first subset of the data interface circuits to be enabled and a second subset of the data interface circuits to be disabled.

### Claim 22 (depends on 21)

The integrated circuit of claim 21, wherein the control packets comprise a first bit field for an opcode.

### Claim 23 (depends on 22)

The integrated circuit of claim 22, wherein the opcode indicates the first subset of the data interface circuits to be enabled and the second subset of the data interface circuits to be disabled.

### Claim 24 (depends on 23)

The integrated circuit of claim 23, wherein the opcode is not associated with a read operation and is not associated with a write operation.

### Claim 25 (depends on 22)

The integrated circuit of claim 22, wherein the control packets comprise a second bit field for the indicator of the first subset of the data interface circuits to be enabled and the second subset of the data interface circuits to be disabled.

### Claim 26 (depends on 25)

The integrated circuit of claim 25, wherein the second bit field is not included in the opcode.

### Claim 27 (depends on 26)

The integrated circuit of claim 26, wherein the second bit field is transmitted in association with a first opcode for a read operation and is transmitted in association with a second opcode for a write operation.

### Claim 28

A memory device, comprising:
a data interface to communicate data with a memory controller using a plurality of data interface circuits; and,
a control interface to receive control packets to from the memory controller using a plurality of control receiver circuits, the control packets including an indicator of a first subset of the data interface circuits to be enabled and a second subset of the data interface circuits to be disabled.

### Claim 29 (depends on 28)

The memory device of claim 28, wherein the control packets comprise a first bit field for an opcode.

### Claim 30 (depends on 29)

The memory device of claim 29, wherein the opcode indicates the first subset of the data interface circuits to be enabled and the second subset of the data interface circuits to be disabled.

### Claim 31 (depends on 30)

The memory device of claim 30, wherein the opcode is not associated with a read operation and is not associated with a write operation.

### Claim 32 (depends on 29)

The memory device of claim 29, wherein the control packets comprise a second bit field for the indicator of the first subset of the data interface circuits to be enabled and the second subset of the data interface circuits to be disabled.

### Claim 33 (depends on 32)

The memory device of claim 32, wherein the second bit field is not included in the opcode.

### Claim 34 (depends on 33)

The memory device of claim 33, wherein the second bit field is received in association with a first opcode for a read operation and is received in association with a second opcode for a write operation.

### Claim 35

A first integrated circuit, comprising:
a data interface to communicate data with a second integrated circuit using a plurality of data links; and,
a control interface to communicate control packets with the second integrated circuit using a plurality of control links, the control packets including an indicator of a first subset of the data links to be enabled and a second subset of the data links to be disabled.

### Claim 36 (depends on 35)

The first integrated circuit of claim 35, wherein the control packets comprise a first bit field for an opcode.

### Claim 37 (depends on 36)

The first integrated circuit of claim 36, wherein a second bit field is communicated in association with a first opcode for a read operation and is communicated in association with a second opcode for a write operation.

### Claim 38 (depends on 37)

The first integrated circuit of claim 37, wherein the second bit field indicates the first subset of the data links to be enabled and the second subset of the data links to be disabled.

### Claim 39 (depends on 36)

The first integrated circuit of claim 36, wherein the opcode indicates the first subset of the data links to be enabled and the second subset of the data links to be disabled.

### Claim 40 (depends on 39)

The first integrated circuit of claim 39, wherein the opcode is not associated with a read operation and is not associated with a write operation.