# US 2020/0401199 A1 · Integrated circuit thermal throttling with workload adapted thermal sensor maximum temperature > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401199 A1 - Document ID: US20200401199A1 - Status: Published application - Kind: A1 - Application number: 16/926,402 - Filed: 2020-07-10 - Published: 2020-12-24 - Earliest claimed: 2015-12-18 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Ameya Limaye - Web page: https://patentgrep.com/patent/US20200401199A1 ## CPC - G06F 1/206: {comprising thermal management} - G06F 1/203: {for portable computers, e.g. for laptops} - G06F 1/324: by lowering clock frequency - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A method and apparatus for integrated circuit (IC) thermal throttling is described. In one embodiment, the apparatus comprises a plurality of thermal sensors, each of the plurality of thermal sensors being located in an area in the IC to record a die temperature at a location in its associated area; and a thermal controller coupled to the plurality of thermal sensors to perform thermal throttling of the IC to reduce the temperature of the IC in response to the die temperature recorded by any one temperature sensors of the plurality of thermal sensors being greater than an individual temperature threshold for said any one temperature sensor, the individual temperature threshold for each temperature sensor being based on a maximum temperature allowed for the area in the IC in which said each thermal sensor is located and power supplied to a plurality of areas of the IC. ## Claims ### Claim 1 (canceled) ### Claim 2 A processor comprising: a plurality of thermal sensors distributed in the processor, wherein an individual thermal sensor has an individual temperature threshold; and a controller coupled to the thermal sensors, wherein the controller is to adaptively modify the individual temperature threshold according to workload executed by the processor. ### Claim 3 (depends on 2) The processor of claim 2, wherein the controller is to adaptively modify the individual temperature threshold in real-time. ### Claim 4 (depends on 2) The processor of claim 2, wherein the controller is to adaptively modify the individual temperature threshold every clock cycle. ### Claim 5 (depends on 2) The processor of claim 2, wherein the controller is to perform thermal throttling of the processor in response to a temperature recorded by any one of the thermal sensors of the plurality of thermal sensors being greater than the individual temperature threshold. ### Claim 6 (depends on 2) The processor of claim 2, wherein the plurality of thermal sensors is distributed in multiple functional blocks including processor cores, pipelines, I/O blocks, and uncore. ### Claim 7 (depends on 2) The processor of claim 2, wherein the individual temperature threshold is based on a maximum temperature allowed for an area of the processor. ### Claim 8 (depends on 7) The processor of claim 7, wherein the individual temperature threshold for each thermal sensor is based on a difference between the maximum temperature allowed for the area in the processor and a power supplied to a plurality of areas of the processor. ### Claim 9 (depends on 7) The processor of claim 7, wherein the individual temperature threshold for each thermal sensor is based on a difference between the maximum temperature allowed for the area in the processor in which said each thermal sensor is located and a sum of a product of each power supplied to each area of a plurality of areas of the processor and a weighting factor associated with said each power supplied to each area. ### Claim 10 (depends on 9) The processor of claim 9, wherein the weighting factor depends upon a distance of a power source from a functional block and the individual thermal sensor. ### Claim 11 (depends on 9) The processor of claim 9, wherein the weighting factor is stored in memory. ### Claim 12 (depends on 2) The processor of claim 2 comprising memory to store the individual temperature threshold. ### Claim 13 (depends on 12) The processor of claim 12 comprising a circuitry to update the individual temperature threshold stored in the memory. ### Claim 14 (depends on 2) The processor of claim 2 wherein the controller is to cause dynamic frequency scaling to perform thermal throttling of the processor. ### Claim 15 A machine-readable media having machine-readable instructions stored thereon, that when executed, cause one or more machines to perform a method comprising: adaptively modifying an individual temperature threshold of an individual thermal sensor according to workload executed by a processor, wherein the individual thermal sensor is from a plurality of thermal sensors distributed in the processor. ### Claim 16 (depends on 15) The machine-readable media of claim 15, wherein adaptively modifying the individual temperature threshold comprises modifying the individual temperature threshold in real-time. ### Claim 17 (depends on 15) The machine-readable media of claim 15, wherein adaptively modifying the individual temperature threshold comprises modifying the individual temperature threshold every clock cycle. ### Claim 18 (depends on 15) The machine-readable media of claim 15 having machine-readable instructions stored thereon, that when executed, cause the one or more machines to perform the method comprising performing thermal throttling of the processor in response to a temperature recorded by any one of the thermal sensors of the plurality of thermal sensors being greater than the individual temperature threshold. ### Claim 19 A system comprising: a memory; a processor coupled to the memory; and a wireless interface to allow the processor to communicate with another device, wherein the processor includes: a plurality of thermal sensors distributed in the processor, wherein an individual thermal sensor has an individual temperature threshold; and a controller coupled to the thermal sensors, wherein the controller is to adaptively modify the individual temperature threshold according to workload executed by the processor. ### Claim 20 (depends on 19) The system of claim 19, wherein the controller is to adaptively modify the individual temperature threshold in real-time. ### Claim 21 (depends on 19) The system of claim 19, wherein the controller is to adaptively modify the individual temperature threshold every clock cycle. ### Claim 22 (depends on 19) The system of claim 19, wherein the controller is to perform thermal throttling of the processor in response to a temperature recorded by any one of the thermal sensors of the plurality of thermal sensors being greater than the individual temperature threshold. ### Claim 23 (depends on 19) The system of claim 19, wherein the plurality of thermal sensors is distributed in multiple functional blocks including processor cores, pipelines, I/O blocks, and uncore. ### Claim 24 (depends on 19) The system of claim 19, wherein the individual temperature threshold is based on a maximum temperature allowed for an area of the processor. ### Claim 25 (depends on 24) The system of claim 24, wherein the individual temperature threshold for each thermal sensor is based on a difference between the maximum temperature allowed for the area in the processor and a power supplied to a plurality of areas of the processor. ### Claim 26 (depends on 24) The system of claim 24, wherein the individual temperature threshold for each thermal sensor is based on a difference between the maximum temperature allowed for the area in the processor in which said each thermal sensor is located and a sum of a product of each power supplied to each area of a plurality of areas of the processor and a weighting factor associated with said each power supplied to each area.