# US 2020/0401179 A1 · Hierarchical clock tree construction based on constraints

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2020/0401179 A1
- Document ID: US20200401179A1
- Status: Published application
- Kind: A1
- Application number: 16/664,791
- Filed: 2019-10-25
- Published: 2020-12-24
- Earliest claimed: 2019-06-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sridhar SUBRAMANIAM; Hongda LU; Kok-Hoong CHIU
- Web page: https://patentgrep.com/patent/US20200401179A1

## CPC

- G06F 30/396: Clock trees
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 30/30: Circuit design
- G06F 30/3312: Timing analysis
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/3947: global
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of automatically constructing a hierarchical clock tree for an integrated circuit may include constructing a global clock tree on a first level based on first-level constraints, pushing the global clock tree to partitions on a second level, and generating second-level constraints for the partitions on the second level. The second-level constraints may be included in configuration files that may be generated for the partitions on the second level. The first-level constraints may be included in a first-level configuration file that is user-modifiable. The second-level constraints may include information for replicating multiple instantiated partitions on the second level. The method may further include modifying terminal names and/or configurations after pushdown. The method may further include creating infrastructure to analyze timing of the global clock tree.

## Claims

### Claim 1

A method of automatically constructing a hierarchical clock tree for an integrated circuit, the method comprising:
constructing a global clock tree on a first level based on first-level constraints;
pushing the global clock tree to partitions on a second level; and
generating second-level constraints for the partitions on the second level.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second-level constraints include information for replicating multiple instantiated partitions on the second level.

### Claim 3 (depends on 1)

The method of claim 1, further comprising modifying terminal names after pushdown.

### Claim 4 (depends on 1)

The method of claim 1, further comprising modifying terminal configurations after pushdown.

### Claim 5 (depends on 1)

The method of claim 1, further comprising generating configuration files including the second-level constraints for the partitions on the second level.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first-level constraints are included in a first-level configuration file that is user-modifiable.

### Claim 7 (depends on 1)

The method of claim 1, further comprising creating infrastructure to analyze timing of the global clock tree.

### Claim 8 (depends on 7)

The method of claim 7, wherein creating the infrastructure comprises replicating cells and routes for multiple instance partitions.

### Claim 9 (depends on 8)

The method of claim 8, wherein creating the infrastructure further comprises adding clock sinks near endpoints of the global clock tree.

### Claim 10 (depends on 9)

The method of claim 9, further comprising calculating timing for the endpoints of the global clock tree based on the first-level constraints.

### Claim 11 (depends on 10)

The method of claim 10 wherein calculating timing for the endpoints comprises calculating latency.

### Claim 12 (depends on 10)

The method of claim 10 wherein calculating timing for the endpoints comprises calculating skew.

### Claim 13 (depends on 1)

The method of claim 1, wherein:
the first level is a top level; and
the second level is a block level.

### Claim 14

(canceled)

### Claim 15 (depends on 1)

The method of claim 1, wherein the method is performed in a user-interactive mode.

### Claim 16

(canceled)

### Claim 17 (depends on 1)

The method of claim 1, wherein constructing a global clock tree on a first level based on first-level constraints comprises:
placing clock cells for the global clock tree on a first level based on the first-level constraints;
modifying a first-level netlist to include new nets for the clock cells; and
routing segments for the global clock tree based on the first-level constraints.

### Claim 18

(canceled)

### Claim 19

A method of automatically constructing a hierarchical clock tree for an integrated circuit, the method comprising:
placing cells for a global clock tree on a first level based on first-level constraints;
routing segments for the global clock tree on the first level based on the first-level constraints;
creating clock routes for multiple instantiated partitions on a second level based on the global clock tree;
pushing the global clock tree to the second level; and
generating second-level constraints for the global clock tree in partitions on the second level, including the multiple instantiated partitions.

### Claim 20 (depends on 19)

The method of claim 19, wherein creating clock routes for multiple instantiated partitions further comprises replicating route segments that cross from non-master to master partitions.

### Claim 21 (depends on 20)

The method of claim 20, wherein creating clock routes for multiple instantiated partitions further comprises renaming route segments that cross from non-master to master partitions.

### Claim 22 (depends on 20)

The method of claim 20, wherein creating clock routes for multiple instantiated partitions further comprises trimming route segments to prevent the route segments from passing into non-master MIM instances.

### Claim 23

A method of constructing a hierarchical clock tree for an integrated circuit, the method comprising:
placing cells in based on a global clock tree distribution topology with constraints;
generating routes based on the global clock tree distribution topology with constraints;
pushing the cells and routes from a first level to partitions on a second level; and
implementing the global clock tree on the second level using engineering change orders (ECOs).

### Claim at position 24

24-26. (canceled)