# US 2020/0401178 A1 · Clock generator for adjusting jitter characteristics and operation power, semiconductor device including the clock generator, and operating method of the clock generator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401178 A1 - Document ID: US20200401178A1 - Status: Published application - Kind: A1 - Application number: 16/724,754 - Filed: 2019-12-23 - Published: 2020-12-24 - Earliest claimed: 2019-06-18 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sangdon Jung; Jaehong Jung; Seunghyun Oh; Kyungmin Lee - Web page: https://patentgrep.com/patent/US20200401178A1 ## CPC - G06F 1/08: Clock generators with changeable or programmable clock frequency - H03L 7/0802: {the loop being adapted for reducing power consumption (H03L7/14 takes precedence)} - H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop - H03L 7/097: using a comparator for comparing the voltages obtained from two frequency to voltage converters - H03L 7/099: concerning mainly the controlled oscillator of the loop - H03L 7/0995: {the oscillator comprising a ring oscillator} - H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract The clock generator is provided and includes a phase detector, a voltage generator, a voltage-to-current converter, and an oscillation circuit. The voltage generator generates a control voltage. The voltage-to-current converter converts the control voltage into an internal current having a level based on a resistance value of a resistor circuit, the resistance value set based on first control information. The oscillation circuit generates a output clock having a frequency based on the level of the internal current and a capacitance value of a capacitor circuit, the capacitance value set based on second control information. The clock generator maintains a frequency value and varies jitter characteristics of the output clock in response to the first control information and the second control information. ## Claims ### Claim 1 A clock generator comprising: a phase detector configured to detect a phase difference between an input clock and a signal obtained by dividing an output clock; a voltage generator configured to generate a control voltage having a level based on the phase difference; a voltage-to-current converter comprising a resistor circuit comprising a plurality of resistors, the voltage-to-current converter being configured to convert the control voltage into an internal current having a level based on a resistance value of the resistor circuit; and an oscillation circuit comprising a capacitor circuit comprising a plurality of capacitors, the oscillation circuit generating the output clock having a frequency based on the level of the internal current and a capacitance value of the capacitor circuit, wherein the clock generator is configured to adjust the resistance value of the resistor circuit based on first control information and the capacitance value of the capacitor circuit based on second control information to maintain a frequency value and vary a jitter characteristic of the output clock. ### Claim 2 (depends on 1) The clock generator of claim 1, wherein the resistor circuit further comprises a plurality of first switches arranged in correspondence with the plurality of resistors, and the capacitor circuit further comprises a plurality of second switches arranged in correspondence with the plurality of capacitors, and as switching of the plurality of first switches is controlled in response to the first control information, the resistance value is set, and as switching of the plurality of second switches is controlled in response to the second control information, the capacitance value is set. ### Claim 3 (depends on 2) The clock generator of claim 2, wherein when the resistance value of the resistor circuit is set to be low, a jitter of the output clock decreases, and when the resistance value of the resistor circuit is set to be high, the jitter of the output clock increases. ### Claim 4 (depends on 1) The clock generator of claim 1, wherein the first control information and the second control information have the same bit value. ### Claim 5 (canceled) ### Claim 6 A clock generator comprising: a phase detector configured to detect a phase difference between an input clock and a signal obtained by dividing an output clock; a voltage generator configured to generate a control voltage having a level based on the phase difference; a voltage-to-current converter comprising a resistor circuit comprising a plurality of resistors, the voltage-to-current converter being configured to convert the control voltage into an internal current having a level based on a resistance value of the resistor circuit, the resistance value being set based on first control information; and an oscillation circuit comprising a capacitor circuit comprising a plurality of capacitors, the oscillation circuit generating the output clock having a frequency based on the level of the internal current and a capacitance value of the capacitor circuit, the capacitance value being set based on second control information; a digital-to-analog converter connected to an output of the voltage-to-current converter to generate a first current having a level proportional to the internal current from the voltage-to-current converter in response to receiving a control bit, wherein the clock generator is configured to maintain a frequency value and vary a jitter characteristic of the output clock in response to the first control information and the second control information, and wherein the oscillation circuit is configured to receive the first current as a supply current from the digital-to-analog converter. ### Claim 7 (depends on 6) The clock generator of claim 6, further comprising an automatic frequency control (AFC) circuit configured to generate the control bit by monitoring the output clock or by monitoring the signal obtained by dividing the output clock, and to provide the control bit to the digital-to-analog converter. ### Claim 8 (depends on 1) The clock generator of claim 1, further comprising a frequency multiplier configured to receive the input clock and multiply a frequency of the input clock to generate a reference clock, wherein the reference clock from the frequency multiplier is provided as an input of the phase detector. ### Claim 9 (depends on 1) The clock generator of claim 1, wherein the voltage-to-current converter further comprises: an amplifier comprising a first input terminal connected to the control voltage and a second input terminal connected to an output terminal of the voltage-to-current converter; and one or more first transistors configured to turn on in response to an output of the amplifier to generate the internal current, and wherein the resistor circuit further comprises a plurality of first switches arranged in correspondence with the plurality of resistors, the plurality of first switches connected to one end of each of the one or more first transistors, and controlled to be switched on or off according to the first control information. ### Claim 10 (depends on 9) The clock generator of claim 9, further comprising a digital-to-analog converter comprising one or more second transistors configuring a current mirror along with the one or more first transistors, and one or more second switches respectively corresponding to the one or more second transistors, the digital-to-analog converter outputting, according to switching-on of the one or more second switches, a first current having a level proportional to the internal current. ### Claim 11 (depends on 10) The clock generator of claim 10, wherein the oscillation circuit comprises a plurality of delay cells, each of the plurality of delay cells receiving the first current as a supply current, and each of the plurality of delay cells comprises the capacitor circuit, the capacitor circuit comprises the plurality of capacitors and a plurality of third switches arranged in correspondence with the plurality of capacitors, and switching of the plurality of third switches is controlled in response to the second control information. ### Claim 12 A semiconductor device comprising: a clock generator configured to receive an input clock to generate an output clock having a target frequency; and a control logic configured to output control information for controlling a jitter characteristic of the output clock of the clock generator, wherein the clock generator comprises a voltage controlled oscillator configured to generate the output clock having a frequency based on a control voltage generated based on a phase difference between the input clock and a signal obtained by dividing the output clock, and wherein the voltage controlled oscillator is configured to receive the control information and decrease a jitter of the output clock having the target frequency in response to the control information having a first value, and to increase the jitter of the output clock having the target frequency in response to the control information having a second value. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the control logic is configured to provide, in a first mode, the clock generator with the control information having the first value, and to provide, in a second mode, the clock generator with the control information having the second value, and the target frequency is constant in the first mode and the second mode. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the first mode corresponds to a low power mode, the first value has a value for increasing the jitter of the output clock, the second mode corresponds to a high power mode, and the second value has a value for decreasing the jitter of the output clock. ### Claim 15 (depends on 12) The semiconductor device of claim 12, wherein the voltage controlled oscillator comprises: a voltage-to-current converter comprising a resistor circuit comprising a plurality of resistors, the voltage-to-current converter being configured to convert the control voltage into an internal current and adjust a resistance value of the resistor circuit on the basis of the control information to adjust a level of the internal current; and an oscillation circuit comprising a capacitor circuit comprising a plurality of capacitors, the oscillation circuit being configured to generate the output clock on the basis of a supply current and adjust a capacitance value of the capacitor circuit on the basis of the control information to adjust the frequency of the output clock. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein the voltage controlled oscillator further comprises a digital-to-analog converter connected to an output of the voltage-to-current converter to generate a first current having a level proportional to the internal current from the voltage-to-current converter in response to receiving a control bit, and the oscillation circuit is configured to receive the first current as the supply current and generate the output clock having a frequency based on the level of the first current and the capacitance value. ### Claim 17 (depends on 15) The semiconductor device of claim 15, wherein the resistor circuit comprises a plurality of first switches arranged in correspondence with the plurality of resistors, the capacitor circuit comprises a plurality of second switches arranged in correspondence with the plurality of capacitors, and the plurality of first switches and the plurality of second switches are controlled based on the control information. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein in response to the control information, when the resistance value of the resistor circuit decreases, the capacitance value of the capacitor circuit increases, and when the resistance value of the resistor circuit decreases, the capacitance value of the capacitor circuit decreases. ### Claim at position 19 19-29. (canceled) ### Claim at position 20 30-31. (canceled) ### Claim 32 (canceled) ### Claim 33 (canceled)