# US 2020/0401094 A1 · Method and system for providing programmable microcontroller unit (mcu) using two-phase configuration process

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- Number: US 2020/0401094 A1
- Document ID: US20200401094A1
- Status: Published application
- Kind: A1
- Application number: 16/988,534
- Filed: 2020-08-07
- Published: 2020-12-24
- Earliest claimed: 2017-05-12
- Assignees: GOWIN Semiconductor Corporation
- Applicants: GOWIN Semiconductor Corporation
- Inventors: Jinghui Zhu
- Web page: https://patentgrep.com/patent/US20200401094A1

## CPC

- G05B 19/042: using digital processors (G05B19/05 takes precedence)
- G05B 19/0426: {Programming the control sequence}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G05B 2219/25257: Microcontroller
- G06F 2213/0016: Inter-integrated circuit (I2C)
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

One embodiment of the present invention discloses a two-phase configuration process (“TCP”) to configure a field-programmable gate array (“FPGA”) to include a configurable microcontroller unit (“CMU”) during a phase I configuration and configuring the CMU during a phase II configuration. TCP, in one aspect, is able to receive first configuration data from a first external storage location via a communication bus. After storing the first configuration data in a first configuration memory for configuring FPGA to contain a CMU for the phase I configuration, second configuration data with MCU attributes is obtained from a second external storage location via the communication bus. The second configuration data is subsequently stored in a second configuration memory for programming the CMU for the phase II configuration.

## Claims

### Claim 1

A method of configuring a field-programmable gate array (“FPGA”) containing a configurable microcontroller unit (“MCU”) via a two-phase configuration process, the method comprising:
receiving first configuration data from a first external storage location via a communication bus;
storing the first configuration data in a first configuration memory for configuring a field-programmable gate array (“FPGA”) containing a configurable microcontroller unit (“MCU”);
obtaining second configuration data with MCU attributes from a second external storage location via the communication bus; and
storing the second configuration data in a second configuration memory for programming the configurable MCU.

### Claim 2 (depends on 1)

The method of claim 1, further comprising programming the FPGA via FPGA configuration data stored in the first configuration memory to behave as an MCU which can be further configured by a user.

### Claim 3 (depends on 2)

The method of claim 2, further comprising configuring the configurable MCU via MCU configuration data stored in the second configuration memory to perform at least one user-defined MCU function when the FPGA is programmed.

### Claim 4 (depends on 1)

The method of claim 1, further comprising identifying a first embedded function of a configurable MCU for facilitating network interface between a host and an external device based on a first interface protocol.

### Claim 5 (depends on 4)

The method of claim 4, further comprising searching a first bit map via a communication network for programming the configurable MCU to perform the first embedded function.

### Claim 6 (depends on 4)

The method of claim 4, further comprising:
downloading the first bit map from a cloud system via a communication network through the communication bus to the second configuration memory; and
programming the configurable MCU in response to the first bit map.

### Claim 7 (depends on 6)

The method of claim 6, further comprising storing the first bit map in a local flash memory.

### Claim 8 (depends on 4)

The method of claim 4, wherein identifying a first embedded function includes determining an inter-integrated circuit (“I2C”) interface function for communicating with at least one external device.

### Claim 9 (depends on 4)

The method of claim 4, wherein identifying a first embedded function includes determining a universal asynchronous receiver-transmitter (“UART”) interface function for communicating with at least one external device.

### Claim 10 (depends on 5)

The method of claim 5, further comprising searching a new bit map associated with the first embedded function for programming the configurable MCU if the first bit map fails to verify the first embedded function performed by the configurable MCU.

### Claim 11 (depends on 6)

The method of claim 6, further comprising:
identifying a second embedded function of the configurable MCU for facilitating network interface between a host and an external device based on a second interface protocol;
downloading the second bit map from the cloud system to the second configuration memory via the communication network through the communication bus; and
programming the configurable MCU in response to the second bit map.

### Claim 12

A programmable logic device (“PLD”) configurable to contain a configurable microcontroller unit (“CMU”) for processing information, the PLD comprising:
an embedded processor able to perform logic functions based on instruction sets;
a plurality of configurable logic blocks (“CLBs”) coupled to the embedded processor and organized by blocks of lookup tables (“LUTs”) able to be programmed to perform user defined logic functions;
a first configuration memory coupled to the plurality of CLBs and configured to store PLD configuration data for configuring the PLD to contain a CMU; and
a second configurable memory coupled to the plurality of CLBs and configured to store CMU configuration data for programming the CMU.

### Claim 13 (depends on 12)

The PLD of claim 12, further comprising an embedded flash memory wherein a portion of the embedded flash memory houses the first configuration memory for PLD configuration and a second portion of the embedded flash memory houses the second configuration memory for CMU configuration.

### Claim 14 (depends on 12)

The PLD of claim 12, further comprising a static random-access memory (“SRAM”) wherein a portion of the SRAM is configured to be the first configuration memory for PLD configuration and a second portion of the SRAM is configured to be the second configuration memory for CMU configuration.

### Claim 15 (depends on 12)

The PLD of claim 12, wherein the processor includes hard macro operable to selectively execute instruction sets based on one of Advanced RISC (reduced instruction set computing) Machine (“ARM”), Million Instructions Per Second (“MIPS”), Argonaut RISC Core (“ARC”), X86, and Power PC in accordance with processor programmable code.

### Claim 16 (depends on 12)

The PLD of claim 12, wherein the plurality of CLBs is configured to behave as a device of CMU having multiple programmable interfaces facilitating communication between a plurality of I/O ports and one or more external devices via at least one of several configurable communication standards in accordance with a set of predefined programming microcode in the second configuration memory.

### Claim 17 (depends on 16)

The PLD of claim 16, wherein the programmable interfaces are configured to utilize inter-integrated circuit (“I2C”) to facilitate communication between the plurality of I/O ports and one or more external devices in accordance with the set of predefined programming microcode.

### Claim 18 (depends on 16)

The PLD of claim 16, wherein the programmable interfaces are configured to employ serial peripheral interface (“SPI”) bus protocol to facilitate communication between the plurality of I/O ports and one or more external devices in accordance with the interface programming microcode.

### Claim 19 (depends on 16)

The PLD of claim 16, wherein the programmable interfaces are configured to employ an improved Inter-Integrated Circuit (“I3C”) bus protocol to facilitate communication between the plurality of I/O ports and one or more external devices in accordance with the interface programming microcode.

### Claim 20 (depends on 16)

The PLD of claim 16, wherein the programmable interfaces are configured to one of utilize universal asynchronous receiver-transmitter (“UART”), Integer (“Int”), two-wire interface (“TWI”), and Timer interface protocol to facilitate communication between the plurality of I/O ports and one or more external devices in accordance with the interface programming microcode.

### Claim 21

A method of configuring a field-programmable gate array (“FPGA”) to contain a configurable microcontroller unit (“MCU”) via a two-phase configuration process, the method comprising:
retrieving first configuration data from a first configuration memory for configuring a field-programmable gate array (“FPGA”);
configuring the FPGA to behave as one or more MCUs in accordance with the first configuration data;
completing a first phase configuration after verifying functionality of the FPGA containing the configurable MCU; and
obtaining second configuration data from a second configuration memory and configuring the configurable MCU in accordance with the second configuration data for performing one or more user-defined MCU logic functions.

### Claim 22 (depends on 21)

The method of claim 21 further comprising verifying functionalities of the configurable MCU.

### Claim 23 (depends on 22)

The method of claim 22 further comprising completing a second phase configuration after one or more user-defined functionalities of the configurable MCU are verified.

### Claim 24 (depends on 21)

The method of claim 21, further comprising identifying a first embedded function of the configurable MCU for facilitating network interface between a host and an external device based on a first interface protocol.

### Claim 25 (depends on 24)

The method of claim 24, wherein identifying a first embedded function includes determining an inter-integrated circuit (“I2C”) interface function for communicating with at least one external device.

### Claim 26 (depends on 24)

The method of claim 24, wherein identifying a first embedded function includes determining an improved Inter-Integrated Circuit (“I3C”) interface function for communicating with at least one external device.