# US 2020/0401005 A1 · Array substrate and manufacturing method thereof, display device

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- Number: US 2020/0401005 A1
- Document ID: US20200401005A1
- Status: Published application
- Kind: A1
- Application number: 16/326,539
- Filed: 2018-06-04
- Published: 2020-12-24
- Earliest claimed: 2017-09-05
- Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Inventors: Xinjie ZHANG; Chengwei LIU
- Web page: https://patentgrep.com/patent/US20200401005A1

## CPC

- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure relates to an array substrate and a manufacturing method thereof, a display device. The manufacturing method of the array substrate includes: upon manufacturing of a gate layer, connecting a gate line in the gate layer with a signal line electrically; and after manufacturing of an active layer is completed, disconnecting electrical connection of the gate line with the signal line.

## Claims

### Claim 1

An array substrate manufacturing method comprising:
forming a gate layer, the gate layer comprises a gate line and a signal line which are connected electrically;
forming an active layer; and
disconnecting electrical connection of the gate line with the signal line after forming the active layer.

### Claim 2 (depends on 1)

The array substrate manufacturing method according to claim 1, wherein forming the gate layer comprises:
forming a connection lead between the gate line and the signal line, two ends of the connection lead connect with the gate line and the signal line respectively.

### Claim 3 (depends on 2)

The array substrate manufacturing method according to claim 2, wherein forming the gate layer comprises forming the gate line and the connection lead simultaneously.

### Claim 4 (depends on 2)

The array substrate manufacturing method according to claim 2, wherein disconnecting electrical connection of the gate line with the signal line comprises:
removing the connection lead.

### Claim 5 (depends on 2)

The array substrate manufacturing method according to claim 2, further comprising:
forming a gate insulation layer on the gate layer, wherein forming a gate insulation layer on the gate layer comprises removing a gate insulation material at a corresponding location of the connection lead and exposing the connection lead; and
forming a source-drain layer on the gate insulation layer, wherein forming a source-drain layer on the gate insulation layer comprises removing the connection lead.

### Claim 6 (depends on 5)

The array substrate manufacturing method according to claim 5, wherein forming a gate insulation layer on the gate layer comprises:
forming a gate insulation material film on the gate layer; and
forming a pattern of the gate insulation layer by a patterning process, the connection lead being exposed at the location of the pattern corresponding to the connection lead.

### Claim 7 (depends on 6)

The array substrate manufacturing method according to claim 6, wherein before forming the gate insulation material film, the method further comprises:
forming a gate material film; and
forming a pattern of the gate layer by a patterning process, the pattern of the gate layer including the connection lead.

### Claim 8 (depends on 7)

The array substrate manufacturing method according to claim 7, wherein after forming the pattern of the gate layer by the patterning process, the method further comprises:
forming an active layer material film; and
forming a pattern of the active layer by a patterning process.

### Claim 9 (depends on 5)

The array substrate manufacturing method according to claim 5, wherein forming a source-drain layer on the gate insulation layer comprises:
forming a source-drain material film; and
forming a pattern of the source-drain layer by a patterning process, and removing the connection lead.

### Claim 10 (depends on 9)

The array substrate manufacturing method according to claim 9, wherein after forming the pattern of the source-drain layer, the method further comprises:
forming an inter-layer insulation layer;
forming a first electrode layer;
forming a passivation layer; and
forming a second electrode layer.

### Claim 11 (depends on 2)

The array substrate manufacturing method according to claim 2, wherein the connection lead bypasses a connection path between a gate drive circuit and the gate line.

### Claim 12 (depends on 11)

The array substrate manufacturing method according to claim 11, wherein the connection path is a linear connection path.

### Claim 13 (depends on 1)

An array substrate which is manufactured by adopting the array substrate manufacturing method of claim 1.

### Claim 14

(canceled)

### Claim 15 (depends on 13)

The array substrate according to claim 13, wherein, forming the gate layer comprises:
forming a connection lead between the gate line and the signal line, two ends of the connection lead connect with the gate line and the signal line respectively.

### Claim 16 (depends on 15)

The array substrate according to claim 15, wherein forming the gate layer comprises forming the gate line and the connection lead simultaneously.

### Claim 17 (depends on 15)

The array substrate according to claim 15, wherein disconnecting electrical connection of the gate line with the signal line comprises:
removing the connection lead.

### Claim 18 (depends on 15)

The array substrate according to claim 15, wherein the connection lead bypasses a connection path between a gate drive circuit and the gate line.

### Claim 19 (depends on 18)

The array substrate according to claim 18, wherein the connection path is a linear connection path.

### Claim 20 (depends on 13)

A display device comprising the array substrate according to claim 13.