# US 2020/0396404 A1 · Image Sensor with Controllable Exposure Response Non-Linearity

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- Number: US 2020/0396404 A1
- Document ID: US20200396404A1
- Status: Published application
- Kind: A1
- Application number: 16/731,999
- Filed: 2019-12-31
- Published: 2020-12-17
- Earliest claimed: 2015-01-26
- Assignees: Trustees of Dartmouth College
- Applicants: Trustees of Dartmouth College
- Inventors: Eric R. Fossum
- Web page: https://patentgrep.com/patent/US20200396404A1

## CPC

- H04N 25/581: acquired simultaneously
- H04N 25/571: involving a non-linear response
- H04N 25/573: {the logarithmic type}
- H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

Some embodiments provide an apparatus and method wherein the non-linearity of the response of a multi-bit QIS is controllable (e.g., selectively variable) by dynamically choosing the bit depth n during A/D conversion, and/or later (i.e., post-conversion) by firmware and/or software.

## Claims

### Claim 1

An image sensor comprising:
an array of pixels, each pixel configured to accumulate photocharge corresponding to photoconversion of photons incident on the pixel;
readout circuitry configured to discriminate individual photocharge, wherein the readout circuitry includes an analog-to-digital converter (ADC) configured to generate a digital signal having a maximum integer bit depth of nmax corresponding to a value of (2nmax−1), and wherein the value of the digital signal output by the readout circuitry for each pixel readout is (i) an integer number equal to the corresponding number of individual accumulated photocharge being readout when the number of individual accumulated photocharge being readout is between 0 and (2nmax−1), inclusive, and (ii) (2nmax−1) when the number of individual accumulated photocharge being readout is greater than (2nmax−1); and
a controller comprising at least one of hardware, software, and firmware configured to selectively adjust the non-linearity of the exposure response of the image sensor, wherein the non-linearity of the exposure response is based on photon arrival statistics; and
wherein the least-significant-bit (LSB) of the ADC corresponds to no more than one photoelectron independent of the non-linearity of the exposure response being selectively adjusted, single-photon sensitivity and resolution thereby being maintained while varying the exposure response.

### Claim 2 (depends on 1)

The image sensor according to claim 1, wherein the controller is configured to selectively adjust the bit depth of the ADC to be an integer value, m, that is less than nmax, such that the value of the digital signal output by the readout circuitry for each pixel readout is (i) an integer number equal to the corresponding number of individual accumulated photocharge being readout when the number of individual accumulated photocharge being readout is between 0 and (2m−1), inclusive, and (ii) (2m−1) when the number of individual accumulated photocharge being readout is greater than (2m−1), thereby selectively adjusting the non-linearity of the exposure response.

### Claim 3 (depends on 1)

The image sensor according to claim 1, wherein the controller is configured to selectively reduce the effective bit depth of digital values output by the ADC to be an integer value, p, that is less than nmax, wherein the value of each of the digital signals output by the ADC (i) is not changed if the digital signal output by the ADC is between 0 and (2p−1), inclusive, and (ii) is adjusted to equal (2p−1) if the digital signal output by the ADC is greater than (2p−1), thereby selectively adjusting the non-linearity of the exposure response.

### Claim 4 (depends on 1)

The image sensor according to claim 1, wherein the image sensor has less than about 0.3 e− rms read noise, and wherein the expected linearity of the image sensor output is determined by the maximum count of the ADC due to Poisson statistics.

### Claim 5 (depends on 1)

The image sensor according to claim 1, wherein the ADC conversion bit depth can be varied by programming the sensor with either on-chip or off-chip electronics.

### Claim 6 (depends on 5)

The image sensor according to claim 5, wherein the image sensor is configured such that the image sensor frame rate is increased and/or the power dissipation of the ADC is reduced upon varying the conversion bit depth.

### Claim 7 (depends on 1)

The image sensor according to claim 1, wherein the image sensor is configured such that the bit depth of the ADC is clipped following conversion to a lesser number of bits to adjust the nonlinearity and overexposure latitude of the response by either hardware or by firmware or software.

### Claim 8 (depends on 1)

The image sensor according to claim 1, wherein the image sensor is configured such that converted pixel signals from a number of successive fields are added together to form an output pixel value, wherein such addition is performed on-chip or off-chip.

### Claim 9 (depends on 1)

The image sensor according to claim 1, wherein the image sensor is configured such that converted pixel signals in a local neighborhood of pixels, as defined for each added field, are digitally summed.

### Claim 10 (depends on 9)

The image sensor according to claim 9, wherein, in the case of the image sensor being configured as a color sensor, the image sensor is configured such that converted pixel signals of the same color are summed.

### Claim 11 (depends on 1)

The image sensor according to claim 1, wherein the controller being configured to selectively adjust the non-linearity of the exposure response includes being configured to selectively increase the non-linearity of the exposure response so as to correspond to an exposure response for the pixels each having a full well capacity of (2n−1), wherein n is a positive integer less than nmax.
