# US 2020/0396378 A1 · Image device and operating method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2020/0396378 A1
- Document ID: US20200396378A1
- Status: Published application
- Kind: A1
- Application number: 16/743,102
- Filed: 2020-01-15
- Published: 2020-12-17
- Earliest claimed: 2019-06-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Ji Un JEONG; Ki Woon KIM; Chae Ryung KIM; Ho Young KIM; Eun Seung YUN; Han Soo LEE; Gyeong Han CHA
- Web page: https://patentgrep.com/patent/US20200396378A1

## CPC

- H04N 23/665: {involving internal camera communication with the image sensor, e.g. synchronising or multiplexing SSIS control signals}
- H04N 23/81: for suppressing or minimising disturbance in the image signal generation
- H03L 7/08: Details of the phase-locked loop
- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H04N 25/617: for reducing electromagnetic interference, e.g. clocking noise
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

An image device may include a clock generator to generate a first output clock of a first frequency, a link layer to generate a control signal for changing the first frequency and output first parallel data including first frame information, a detector to generate a collision avoidance command to change the first frequency to a second frequency during a vertical blanking time, and a frequency changer to receive the collision avoidance command from the detector and transmit a frequency change command to the link layer. The link layer transmits the control signal to the clock generator based on the frequency change command. The vertical blanking time is a time period from a first time point at which the first parallel data is not output from the link layer to a second time point at which second parallel data is output.

## Claims

### Claim 1

An image device, comprising:
a clock generator to generate a first output clock of a first frequency;
a link layer to generate a control signal for changing the first frequency and output first parallel data including first frame information;
a detector to generate a collision avoidance command to change the first frequency to a second frequency during a vertical blanking time, the second frequency being different from the first frequency; and
a frequency changer to receive the collision avoidance command from the detector and transmit a frequency change command to the link layer, wherein:
the link layer transmits the control signal to the clock generator based on the frequency change command, and
the vertical blanking time is a time period from a first time point at which the first parallel data is not output from the link layer to a second time point at which second parallel data is output, the second parallel data including second frame information subsequent to the first frame information.

### Claim 2 (depends on 1)

The image device as claimed in claim 1, wherein
the clock generator includes a phase-locked loop (PLL) circuit and a clock gating circuit, and wherein:
the PLL circuit generates a first PLL clock of the first frequency, and
the clock gating circuit generates the first output clock by controlling output of the first PLL clock.

### Claim 3 (depends on 2)

The image device as claimed in claim 2, wherein
the control signal includes a frequency division control signal and a clock enable signal, and wherein:
the frequency division control signal changes the first frequency of the first PLL clock to the second frequency, and
when the clock enable signal is deactivated, the first PLL clock is blocked by the clock gating circuit such that the first output clock is not output.

### Claim 4 (depends on 3)

The image device as claimed in claim 3, wherein the clock gating circuit includes an inverter, a selector, a first flip-flop, and a second flip-flop, wherein:
the inverter receives the first PLL clock and outputs an inverted first PLL clock,
the first flip-flop receives the clock enable signal via a first input terminal of the first flip-flop and receives the inverted first PLL clock via a second input terminal of the first flip-flop,
the second flip-flop includes a third input terminal connected to a first output terminal of the first flip-flop, receives the inverted first PLL clock via a fourth input terminal of the second flip-flop, and outputs a selection signal via a third output terminal of the second flip-flop, and
the selector receives the first PLL clock via a first input selection terminal of the selector, receives a ground voltage via a second input selection terminal of the selector, selects one of the first PLL clock and the ground voltage, and outputs the selected one as the first output clock.

### Claim 5 (depends on 3)

The image device as claimed in claim 3, wherein:
the clock enable signal is deactivated at the second time point when is later than the first time point by a first period,
the frequency division control signal changes the first frequency of the first PLL clock at a third time point when is later than the second time point by a second period, and
the clock enable signal is activated at a fourth time point when is later than the third time point by a third period.

### Claim 6 (depends on 5)

The image device as claimed in claim 5, wherein:
the link layer is operated based on a first word clock, and
the first period is thirty times of a clock cycle of the first word clock.

### Claim 7 (depends on 5)

The image device as claimed in claim 5, wherein the third period is 75 microseconds or more.

### Claim 8 (depends on 1)

The image device as claimed in claim 1, further comprising a first peripheral circuit to operate in a first bandwidth, wherein
the detector senses whether there is frequency collision between the first frequency and the first bandwidth and transmits the collision avoidance command to the frequency changer when the frequency collision is sensed.

### Claim 9 (depends on 8)

The image device as claimed in claim 8, wherein the second frequency does not collide with the first bandwidth.

### Claim 10

An image device, comprising:
a detector to generate a collision avoidance command;
a frequency changer to receive the collision avoidance command from the detector and generate a frequency change command;
a link layer to receive the frequency change command from the frequency changer, generate a control signal based on the frequency change command, and output first parallel data including first frame information; and
a clock generator to receive the control signal from the link layer and generate a first output clock of a first frequency, wherein:
the first frequency is changed to a second frequency during a vertical blanking time, the second frequency being different from the first frequency, and
the vertical blanking time is a time period from a first time point at which the first parallel data is not output from the link layer to a second time point at which second parallel data is output, the second parallel data including second frame information subsequent to the first frame information.

### Claim 11 (depends on 10)

The image device as claimed in claim 10, wherein
the clock generator includes a phase-locked loop (PLL) circuit and a clock gating circuit, wherein:
the PLL circuit generates a first PLL clock of the first frequency,
the clock gating circuit generates the first output clock by controlling output of the first PLL clock, and
the control signal includes a frequency division control signal and a clock enable signal, and wherein:
the frequency division control signal changes the first frequency of the first PLL clock, and
when the clock enable signal is deactivated, the first PLL clock is blocked by the clock gating circuit such that the first output clock is not output.

### Claim 12 (depends on 11)

The image device as claimed in claim 11, wherein the clock gating circuit includes an inverter, a selector, a first flip-flop, and a second flip-flop, and wherein:
the inverter receives the first PLL clock and outputs an inverted first PLL clock,
the first flip-flop receives the clock enable signal via a first input terminal of the first flip-flop and receives the inverted first PLL clock via a second input terminal of the first flip-flop,
the second flip-flop includes a third input terminal connected to a first output terminal of the first flip-flop, receives the inverted first PLL clock via a fourth input terminal of the second flip-flop, and outputs a selection signal via a third output terminal of the second flip-flop, and
the selector receives the first PLL clock via a first input selection terminal, receives a ground voltage via a second input selection terminal of the selector, and selects one of the first PLL clock and the ground voltage, and outputs the selected one as the first output clock.

### Claim 13 (depends on 11)

The image device as claimed in claim 11, wherein the clock enable signal is deactivated at a second time point when is later than the first time point by a first period, and
the frequency division control signal changes the first frequency of the first PLL clock at a third time point when is later than the second time point by a second period, and
the clock enable signal is activated at a fourth time point when is later than the third time point by a third period.

### Claim 14 (depends on 13)

The image device as claimed in claim 13, wherein:
the link layer is operated based on a first word clock, and
the first period is thirty times of a clock cycle of the first word clock.

### Claim 15 (depends on 13)

The image device as claimed in claim 13, wherein the third period is 75 microseconds or more.

### Claim 16 (depends on 10)

The image device as claimed in claim 10, further comprising a first peripheral circuit to operate at a first bandwidth, wherein:
the detector senses whether there is frequency collision between the first frequency and the first bandwidth, and transmits the collision avoidance command to the frequency changer when the frequency collision is sensed, and
the second frequency does not collide with the first bandwidth.

### Claim 17

An image device, comprising:
a link layer to generate first parallel data including first frame information, the first parallel data being not generated from a first time point;
a first peripheral circuit to operate at a first bandwidth;
a clock generator to generate a first output clock of a first frequency;
a detector to sense whether there is frequency collision between the first bandwidth and the first frequency and generate a collision avoidance command when the frequency collision is sensed; and
a frequency changer to receive the collision avoidance command from the detector and generate a frequency change command to change the first frequency to a second frequency after the first time point, the second frequency not colliding with the first bandwidth.

### Claim 18 (depends on 17)

The image device as claimed in claim 17, wherein the clock generator includes a phase-locked loop (PLL) circuit and a clock gating circuit, wherein:
the PLL circuit generates a first PLL clock operating at the first frequency,
the clock gating circuit generates the first output clock by controlling output of the first PLL clock, and
the link layer generates a control signal, the control signal including a frequency division control signal and a clock enable signal, wherein:
when the clock enable signal is deactivated, the first PLL clock is blocked by the clock gating circuit such that the first output clock is not output at a second time point when is later than the first time point by a first period, and
the frequency division control signal changes the first frequency of the first PLL clock to the second frequency at a third time point when is later than the second time point by a second period.

### Claim 19 (depends on 18)

The image device as claimed in claim 18, wherein:
the link layer is operated based on a first word clock,
the first period is thirty times of a clock cycle of the first word clock,
the clock enable signal is activated at a fourth time point when is later than the third time point by a third period, and
the third period is 75 microseconds or more.

### Claim 20 (depends on 17)

The image device as claimed in claim 17, further comprising a first peripheral circuit to operate in a first bandwidth, wherein:
the detector senses whether there is frequency collision between the first frequency and the first bandwidth and transmits the collision avoidance command to the frequency changer when the frequency collision is sensed,
the second frequency does not collide with the first bandwidth,
the clock generator includes a phase-locked loop (PLL) circuit and a clock gating circuit, and wherein:
the PLL circuit generates a first PLL clock operating at the first frequency,
the clock gating circuit generates the first output clock by controlling the first PLL clock,
the link layer generates a control signal, the control signal including a frequency division control signal and a clock enable signal,
the clock enable signal is deactivated, the first PLL clock is blocked by the clock gating circuit such that the first output clock is not output at a second time point when is later than the first time point by a first period, and
the frequency division control signal changes the first frequency of the first PLL clock to the second frequency at a third time point when is later than the second time point by a second period.