# US 2020/0395752 A1 · Electrostatic discharge circuit

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- Number: US 2020/0395752 A1
- Document ID: US20200395752A1
- Status: Published application
- Kind: A1
- Application number: 16/897,484
- Filed: 2020-06-10
- Published: 2020-12-17
- Earliest claimed: 2019-06-14
- Assignees: eMemory Technology Inc.
- Applicants: eMemory Technology Inc.
- Inventors: Chih-Wei LAI; Yun-Jen TING; Yi-Han WU; Kun-Hsin LIN; Hsin-Kun HSU
- Web page: https://patentgrep.com/patent/US20200395752A1

## CPC

- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- G06F 7/588: {Random number generators, i.e. based on natural stochastic processes}
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- H10D 89/611: {using diodes as protective elements}
- H10D 89/815: {involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor}
- H10B 41/40: characterised by the peripheral circuit region
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An ESD circuit includes a voltage division circuit, a RC control circuit and a voltage selection circuit. The voltage division circuit is connected between a first power pad and a first node, and generates a first voltage. The RC control circuit is connected between the first power pad and a second power pad, and generates a second voltage and a third voltage. The voltage selection circuit receives the first voltage and the second voltage, and outputs a fourth voltage. The first transistor and the second transistor are serially connected between the first power pad and the second power pad. A gate terminal of the first transistor receives the first voltage. A gate terminal of the second transistor receives the third voltage. The third transistor is connected with the first power pad and an internal circuit. A gate terminal of the third transistor receives the fourth voltage.

## Claims

### Claim 1

An electrostatic discharge (ESD) circuit connected with an internal circuit, the ESD circuit comprising:
a first voltage division circuit connected between a first power pad and a first node, wherein the first voltage division circuit generates a first voltage;
a RC control circuit connected between the first power pad and a second power pad, wherein the RC control circuit generates a second voltage and a third voltage;
a voltage selection circuit connected with the first node and the RC control circuit, wherein the voltage selection circuit receives the first voltage and the second voltage, and outputs a fourth voltage, wherein if the first voltage is higher than the second voltage, the fourth voltage is equal to the first voltage, wherein if the second voltage is higher than the first voltage, the fourth voltage is equal to second voltage;
a first transistor, wherein a first terminal of the first transistor is connected with the first power pad, a second terminal of the first transistor is connected with a second node, and a gate terminal of the first transistor receives the first voltage;
a second transistor, wherein a first terminal of the second transistor is connected with the second node, a second terminal of the second transistor is connected with the second power pad, and a gate terminal of the second transistor receives the third voltage; and
a third transistor, wherein a first terminal of the third transistor is connected with the first power pad, a second terminal of the third transistor is connected with the internal circuit, and a gate terminal of the third transistor receives the fourth voltage.

### Claim 2 (depends on 1)

The ESD circuit as claimed in claim 1, wherein when the first power pad receives a positive ESD zap, the first transistor is turned on in response to the first voltage, the second transistor is turned on in response to the third voltage, and the third transistor is turned off in response to the fourth voltage, wherein the fourth voltage is equal to the second voltage.

### Claim 3 (depends on 2)

The ESD circuit as claimed in claim 2, wherein when the first power pad receives the positive ESD zap, an ESD current flows from the first power pad to the second power pad through the first transistor and the second transistor.

### Claim 4 (depends on 1)

The ESD circuit as claimed in claim 1, further comprising a parasitic device connected between the first power pad and the second power pad.

### Claim 5 (depends on 4)

The ESD circuit as claimed in claim 4, wherein the first transistor has a first parasitic diode, the second transistor has a second parasitic diode, and the first parasitic diode and the second parasitic diode form the parasitic device, wherein a cathode of the first parasitic diode is connected with the first power pad, an anode of the first parasitic diode is connected with the second node, a cathode of the second parasitic diode is connected with the second node, and an anode of the second parasitic diode is connected with the second power pad.

### Claim 6 (depends on 4)

The ESD circuit as claimed in claim 4, wherein when the first power pad receives a negative ESD zap, an ESD current flows from the second power pad to the first power pad through the parasitic device.

### Claim 7 (depends on 1)

The ESD circuit as claimed in claim 1, wherein the first voltage division circuit comprises plural diodes, which are serially connected between the first power pad and the first node, wherein the first node generates the first voltage.

### Claim 8 (depends on 7)

The ESD circuit as claimed in claim 7, wherein an anode of a first diode of the plural diodes is connected with the first power pad, and a cathode of a last diode of the plural diodes is connected with the first node, wherein an anode of any other diode between the first diode and the last diode is connected with a cathode of a previous diode, and a cathode of any other diode between the first diode and the last diode is connected with an anode of a next diode.

### Claim 9 (depends on 1)

The ESD circuit as claimed in claim 1, wherein the RC control circuit comprises:
a first resistor, wherein a first terminal of the first resistor is connected with the first power pad, and a second terminal of the first resistor is connected with a third node;
a capacitor bank, wherein a first terminal of the capacitor bank is connected with the third node, and a second terminal of the capacitor bank is connected with the second power pad;
a fourth transistor, wherein a first terminal of the fourth transistor is connected with the first power pad, a second terminal of the fourth transistor is connected with a fourth node, and a gate terminal of the fourth transistor is connected with the third node, wherein the fourth node generates the second voltage;
a second voltage division circuit connected between the fourth node and a fifth node, wherein the fifth node generates the third voltage; and
a second resistor, wherein a first terminal of the second resistor is connected with the fifth node, and a second terminal of the second resistor is connected with the second power pad.

### Claim 10 (depends on 9)

The ESD circuit as claimed in claim 9, wherein the second voltage division circuit comprises plural diodes, wherein are serially connected between the fourth node and the fifth node.

### Claim 11 (depends on 10)

The ESD circuit as claimed in claim 10, wherein an anode of a first diode of the plural diodes is connected with the fourth node, and a cathode of a last diode of the plural diodes is connected with the fifth node, wherein an anode of any other diode between the first diode and the last diode is connected with a cathode of a previous diode, and a cathode of any other diode between the first diode and the last diode is connected with an anode of a next diode.

### Claim 12 (depends on 1)

The ESD circuit as claimed in claim 1, wherein the voltage selection circuit comprises:
a fifth transistor, wherein a first terminal of the fifth transistor receives the second voltage, a second terminal of the fifth transistor is connected with a sixth node, and a gate terminal of the fifth transistor is connected with the first node, wherein the sixth node generates the fourth voltage; and
a sixth transistor, wherein a first terminal of the sixth transistor is connected with the first node, a second terminal of the sixth transistor is connected with the sixth node, and a gate terminal of the sixth transistor receives the second voltage.