# US 2020/0395385 A1 · A semiconductor device and a method for forming the semiconductor device

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- Number: US 2020/0395385 A1
- Document ID: US20200395385A1
- Status: Published application
- Kind: A1
- Application number: 16/438,574
- Filed: 2019-06-12
- Published: 2020-12-17
- Earliest claimed: 2019-06-12
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Bo YU; Shaoqiang ZHANG
- Web page: https://patentgrep.com/patent/US20200395385A1

## CPC

- H10D 30/721: {having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET (TFTs having gate-to-body connection H10D30/6708)}
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/0278: {forming single crystalline channels on wafers after forming insulating device isolations}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6743: {Silicon}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 30/674: {characterised by the active materials}
- H10W 20/0698: {Local interconnections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device may include a semiconductor-on-insulator (SOI) structure that may include a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer. The semiconductor layer may include a first conductivity region and a second conductivity region at least partially arranged within the semiconductor layer. The device may further include a gate structure arranged over the semiconductor layer and between the first conductivity region and the second conductivity region; a first conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate; a second conductor element arranged to electrically contact the gate structure; and a conducting member connecting the first conductor element and the second conductor element to electrically couple the first conductor element and the second conductor element.

## Claims

### Claim 1

A device comprising:
a semiconductor-on-insulator (SOI) structure comprising a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer, wherein the semiconductor layer comprises a first conductivity region and a second conductivity region at least partially arranged within the semiconductor layer;
a gate structure arranged over the semiconductor layer and between the first conductivity region and the second conductivity region;
a first conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate;
a second conductor element arranged to electrically contact the gate structure; and
a conducting member connecting the first conductor element and the second conductor element to electrically couple the first conductor element and the second conductor element.

### Claim 2 (depends on 1)

The device according to claim 1, wherein a diameter of the first conductor element is greater than a diameter of the second conductor element.

### Claim 3 (depends on 1)

The device according to claim 1, wherein the semiconductor layer of the SOI structure further comprises an isolation region at least partially arranged therein; and wherein the first conductor element is arranged through the isolation region.

### Claim 4 (depends on 3)

The device according to claim 3, wherein the isolation region extends at least partially into the insulator layer.

### Claim 5 (depends on 1)

The device according to claim 1, further comprising a third conductor element arranged to electrically contact the second conductivity region; and wherein the third conductor element is electrically isolated from the first conductor element and the second conductor element.

### Claim 6 (depends on 1)

The device according to claim 1, further comprising a fourth conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate, wherein the fourth conductor element is electrically isolated from the first conductor element and the second conductor element.

### Claim 7 (depends on 1)

The device according to claim 1, further comprising a fifth conductor element arranged to electrically contact the first conductivity region; and wherein the fifth conductor element is electrically isolated from the first conductor element and the second conductor element.

### Claim 8 (depends on 1)

The device according to claim 1, wherein the device is a RF switch transistor, a single pole multiple throw switch or a multiple pole multiple throw switch.

### Claim 9

A method comprising:
providing a semiconductor-on-insulator (SOI) structure comprising a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer;
forming a first conductivity region and a second conductivity region at least partially within the semiconductor layer;
forming a gate structure over the semiconductor layer and between the first conductivity region and the second conductivity region;
forming a first conductor element through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate;
forming a second conductor element to electrically contact the gate structure; and
forming a conducting member to connect the first conductor element and the second conductor element to electrically couple the first conductor element and the second conductor element.

### Claim 10 (depends on 9)

The method according to claim 9, wherein a diameter of the first conductor element is greater than a diameter of the second conductor element.

### Claim 11 (depends on 9)

The method according to claim 9, further comprising forming an isolation region at least partially within the semiconductor layer of the SOI structure; and wherein forming the first conductor element comprises forming the first conductor element through the isolation region.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the isolation region extends at least partially into the insulator layer.

### Claim 13 (depends on 9)

The method according to claim 9, wherein forming the first conductor element comprises a first mask and forming the second conductor element comprises a second mask, and wherein the first mask is different from the second mask.

### Claim 14 (depends on 13)

The method according to claim 13, wherein forming the first conductor element and the second conductor element comprises:
forming a first opening for the first conductor element with the first mask; and
forming a second opening for the second conductor element with the second mask, and
depositing conductive material into the first opening and the second opening simultaneously to form the first conductor element and the second conductor element, respectively.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the method further comprises:
forming an insulating layer over the semiconductor layer such that the gate structure is arranged at least partially within the insulating layer;
forming the first mask by depositing a first mask material over the insulating layer; and
forming the second mask by depositing a second mask material over the insulating layer and into the first opening.

### Claim 16 (depends on 9)

The method according to claim 9, further comprising forming a third conductor element to electrically contact the second conductivity region, and wherein the third conductor element is electrically isolated from the first conductor element and the second conductor element.

### Claim 17 (depends on 9)

The method according to claim 9, further comprising forming a fourth conductor element through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate, wherein the fourth conductor element is electrically isolated from the first conductor element and the second conductor element.

### Claim 18 (depends on 9)

The method according to claim 9, further comprising forming a fifth conductor element to electrically contact the first conductivity region, wherein the fifth conductor element is electrically isolated from the first conductor element and the second conductor element.

### Claim 19

A structure comprising a plurality of devices, wherein one or more of the devices comprises:
a semiconductor-on-insulator (SOI) structure comprising a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer, wherein the semiconductor layer comprises a first conductivity region and a second conductivity region at least partially arranged within the semiconductor layer;
a gate structure arranged over the semiconductor layer and between the first conductivity region and the second conductivity region;
a first conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate;
a second conductor element arranged to electrically contact the gate structure; and
a conducting member connecting the first conductor element and the second conductor element to electrically couple the first conductor element and the second conductor element.

### Claim 20 (depends on 19)

The structure according to claim 19, wherein the one or more of the devices comprises a RF switch transistor, a single pole multiple throw switch, a multiple pole multiple throw switch or combinations thereof.