# US 2020/0395084 A1 · Semiconductor storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0395084 A1 - Document ID: US20200395084A1 - Status: Published application - Kind: A1 - Application number: 16/802,471 - Filed: 2020-02-26 - Published: 2020-12-17 - Earliest claimed: 2019-06-11 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Rieko FUNATSUKI; Takashi MAEDA; Hidehiro SHIGA; Hiroshi MAEJIMA - Web page: https://patentgrep.com/patent/US20200395084A1 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/28: using differential sensing or reference cells, e.g. dummy cells - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures} - G11C 16/32: Timing circuits - G11C 27/024: {using a capacitive memory element (G11C27/04 takes precedence)} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node. ## Claims ### Claim 1 A semiconductor storage device comprising: a first memory cell and a second memory cell which are connected to each other in series; a first word line which is connected to the first memory cell; a second word line which is connected to the second memory cell; and a control circuit, wherein the control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node. ### Claim 2 (depends on 1) The semiconductor storage device according to claim 1, wherein the third voltage is higher than the first voltage and lower than the second voltage. ### Claim 3 (depends on 2) The semiconductor storage device according to claim 2, wherein the first voltage is a negative voltage. ### Claim 4 (depends on 1) The semiconductor storage device according to claim 1, wherein the control circuit is configured to charge the second node and then discharge the second node. ### Claim 5 (depends on 4) The semiconductor storage device according to claim 4, wherein a first period in which the second node is charged is longer than a second period in which the second node is discharged. ### Claim 6 (depends on 4) The semiconductor storage device according to claim 4, wherein the first period in which the second node is charged is equal to the second period in which the second node is discharged. ### Claim 7 (depends on 1) The semiconductor storage device according to claim 1, wherein the control circuit is configured to discharge the second node while charging the second node. ### Claim 8 (depends on 1) The semiconductor storage device according to claim 1, wherein the control circuit includes a first transistor which connects the first node to the first memory cell and the second memory cell, a second transistor which includes a first end connected to the first node and a second end connected to a third node, a third transistor which includes a first end connected to the third node, a grounded second end, and a gate connected to the first node, a fourth transistor which includes a first end connected to the second node and a second end connected to the third node, and a fifth transistor which connects the second node to the first memory cell and the second memory cell. ### Claim 9 (depends on 8) The semiconductor storage device according to claim 8, wherein the third transistor has a polarity different from polarities of the first transistor, the second transistor, the fourth transistor, and the fifth transistor. ### Claim 10 (depends on 8) The semiconductor storage device according to claim 8, wherein the control circuit further includes a first capacitor which is connected to the first node, and a second capacitor which is connected to the second node. ### Claim 11 (depends on 8) The semiconductor storage device according to claim 8, wherein the control circuit is configured to charge the first node by setting the fourth transistor and the fifth transistor to be in an off state while setting the first transistor, the second transistor, and the third transistor to be in an on state, to charge the second node by setting the first transistor and the second transistor to be in an off state while setting the third transistor and the fourth transistor to be in an on state, and to discharge the second node by setting the first transistor and the second transistor to be in an off state while setting the fifth transistor to be in an on state. ### Claim 12 (depends on 8) The semiconductor storage device according to claim 8, wherein the control circuit further includes a fifth transistor including a first end connected to a third node and a gate connected to the second node and is configured to apply equal voltages to the third node before the second node is charged and after the second node is discharged. ### Claim 13 (depends on 8) The semiconductor storage device according to claim 8, wherein the control circuit further includes a fifth transistor including a first end connected to a third node and a gate connected to the second node and is configured to apply a fourth voltage to the third node before the second node is charged and to apply a fifth voltage lower than the fourth voltage to the third node after the second node is discharged. ### Claim 14 (depends on 1) The semiconductor storage device according to claim 1, further comprising: a third memory cell which is connected to the first memory cell in parallel with respect to the second memory cell; a fourth memory cell which is connected to the second memory cell in parallel with respect to the first memory cell and connected to the third memory cell in series; a third word line which is connected to the third memory cell; and a fourth word line which is connected to the fourth memory cell, wherein the third memory cell and the fourth memory cell share a well region with the first memory cell and the second memory cell and are arranged so that the well region is interposed therebetween. ### Claim 15 (depends on 14) The semiconductor storage device according to claim 14, wherein the control circuit is configured to charge the first node while applying the second voltage to the second word line, the third word line, and the fourth word line and the first voltage to the first word line, and to discharge the second node while applying the second voltage to the second word line, the third word line, and the fourth word line and a third voltage to the first word line. ### Claim 16 (depends on 14) The semiconductor storage device according to claim 14, wherein the control circuit is configured to charge the first node while applying the second voltage to the second word line and the fourth word line and the first voltage to the first word line and the third word line, and to discharge the second node while applying a third voltage to the first word line, the second voltage to the second word line and the fourth word line, and the first voltage to the third word line. ### Claim 17 (depends on 14) The semiconductor storage device according to claim 14, wherein the control circuit is configured to charge the first node while applying the second voltage to the second word line and the first voltage to the first word line, the third word line, and the fourth word line, and to discharge the second node while applying a third voltage to the first word line, the second voltage to the second word line, and the first voltage to the third word line and the fourth word line. ### Claim 18 (depends on 14) The semiconductor storage device according to claim 14, wherein the control circuit is configured to charge the first node while applying the second voltage to the second word line and the third word line and the first voltage to the first word line and the fourth word line, and to discharge the second node while applying a third voltage to the first word line, the second voltage to the second word line and the third word line, and the first voltage to the fourth word line, and the fourth memory cell is provided between the third memory cell and a bit line. ### Claim 19 (depends on 14) The semiconductor storage device according to claim 14, wherein the control circuit is configured to charge the first node while applying the second voltage to the second word line and applying the first voltage to the first word line, the third word line, and the fourth word line, and to discharge the second node while applying a third voltage to the first word line, the second voltage to the second word line, and the first voltage to the third word line and the fourth word line, and the fourth memory cell is provided between the third memory cell and a bit line. ### Claim 20 A method of performing a read operation in a semiconductor storage device that includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, and a second word line which is connected to the second memory cell, said method comprising: charging a first node while applying a second voltage to the second word line and a first voltage to the first word line; charging a second node on the basis of a voltage of the charged first node; discharging the second node while applying the second voltage to the second word line and a third voltage to the first word line, wherein the third voltage is greater than the first voltage and less than the second voltage; and reading data from the first memory cell on the basis of voltages of the charged and discharged second node.