# US 2020/0395083 A1 · Sensing circuit of memory device and associated sensing method

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- Number: US 2020/0395083 A1
- Document ID: US20200395083A1
- Status: Published application
- Kind: A1
- Application number: 17/008,746
- Filed: 2020-09-01
- Published: 2020-12-17
- Earliest claimed: 2018-12-17
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Chun-Hsiung HUNG
- Web page: https://patentgrep.com/patent/US20200395083A1

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/30: Power supply circuits
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A sensing circuit, a sensing method and a memory device are provided. The sensing method is applied to the memory device having the sensing circuit. The sensing circuit includes a compensation source and a sensing module. The compensation source is capable of providing a compensating current to a first node during a read cycle. The sensing module is coupled to the first node. A cell of the memory device is coupled to the first node. The cell is capable of generating a cell current during the read cycle, and the sensing module determines that the cell is in a first storing state or a second storing state in response to a relationship between the compensating current and the cell current.

## Claims

### Claim 1

A memory device, comprising:
plural first transistors;
plural cells; and
a sensing circuit coupled to the cells through the corresponding first transistors,
wherein the sensing circuit comprises a current mirror and plural sensing modules,
wherein an adjustable current source of the current mirror is coupled to a first node; a first sensing module of the sensing circuit is coupled to the first node; and one of the plural first transistors is coupled between the first node and a first cell of the plural cells.

### Claim 2 (depends on 1)

The memory device as claimed in claim 1, wherein a first sensing module of the sensing circuit comprises:
a second transistor, wherein a first source/drain terminal of the second transistor is coupled to a second node, a second source/drain terminal of the second transistor is coupled to a ground terminal, and a gate terminal of the second transistor is coupled to a third node;
a third transistor, wherein a first source/drain terminal of the third transistor is coupled to the first node, a second source/drain terminal of the third transistor is coupled to the third node, and a gate terminal of the third transistor receives a second control signal;
a fourth transistor, wherein a first source/drain terminal of the fourth transistor is coupled to a supply terminal, a second source/drain terminal of the fourth transistor is coupled to the third node, and a gate terminal of the fourth transistor receives a third control signal;
a capacitor, wherein a first terminal of the capacitor is coupled to the third node, and a second terminal of the capacitor is coupled to the ground terminal;
a fifth transistor, wherein a first source/drain terminal of the fifth transistor is coupled to the second node, a second source/drain terminal of the fifth transistor is coupled to a fourth node, and a gate terminal of the fifth transistor receives a fourth control signal; and
a latch coupled to the fourth node.

### Claim 3 (depends on 1)

The memory device as claimed in claim 1, wherein the current mirror comprises:
the adjustable current source including a sixth transistor, wherein a first source/drain terminal of the sixth transistor is coupled to the supply terminal, a second source/drain terminal of the sixth transistor is coupled to the node BLI, and a gate terminal of the sixth transistor;
a seventh transistor, wherein a first source/drain terminal of the seventh transistor is coupled to the supply terminal, and a second source/drain terminal of the seventh transistor is coupled to a gate terminal of the seventh transistor and the gate terminal of the sixth transistor;
an eighth transistor, wherein a first source/drain terminal of the eighth transistor is coupled to the supply terminal, a second source/drain terminal of the eighth transistor is coupled to the gate terminal of the seventh transistor, and a gate terminal of the eighth transistor receives a fifth control signal;
a ninth transistor, wherein a first source/drain terminal of the ninth transistor is coupled to the gate terminal of the seventh transistor, and a gate terminal of the ninth transistor receives the fifth control signal; and
a reference current source, wherein a first terminal of the reference current source is coupled to a second source/drain terminal of the ninth transistor, and a second terminal of the reference current source is coupled to the ground terminal.

### Claim 4 (depends on 1)

The memory device as claimed in claim 1, wherein a reference current generated by the reference current source is proportional to a compensating current generated by the adjustable current source.

### Claim 5 (depends on 1)

The memory device as claimed in claim 1, wherein a first source/drain terminal of the one of the plural first transistors is coupled to the first node, a second source/drain terminal of the one of the plural first transistors is coupled to a first terminal of the first cell, a gate terminal of the first transistor receives a first control signal, a second terminal of the first cell is coupled to the ground terminal, and a control terminal of the first cell receives a word line signal.

### Claim 6 (depends on 1)

The memory device as claimed in claim 1, wherein a compensating current generated by the adjustable current source is less than a first cell current generated by the first cell in a first storing state, and the compensating current is greater than a second cell current generated by the first cell in a second storing state.