# US 2020/0394355 A1 · Method of fabricating a semiconductor device

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- Number: US 2020/0394355 A1
- Document ID: US20200394355A1
- Status: Published application
- Kind: A1
- Application number: 17/007,727
- Filed: 2020-08-31
- Published: 2020-12-17
- Earliest claimed: 2010-09-10
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Annie LUM; Derek C. TAO; Cheng Hung LEE; Chung-Ji LU; Hong-Chen CHENG; Vineet Kumar AGRAWAL; Keun-Young KIM; Pyong Yun CHO
- Web page: https://patentgrep.com/patent/US20200394355A1

## CPC

- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- H10D 89/10: Integrated device layouts
- Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

## Claims

### Claim 1

A method of fabricating an integrated circuit, comprising:
identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions;
modifying the first layout resulting in a second layout comprising:
adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region;
adding a dummy gate structure next to the dummy device;
extending the shared diffusion region to at least the dummy device; and
performing a design rule check on the second layout, the performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device; and
fabricating the integrated circuit based on the second layout.

### Claim 2 (depends on 1)

The method of claim 1, wherein modifying the first layout resulting in the second layout further comprises:
adding an additional diffusion region on a first side of the dummy device opposite from a second side of the dummy device adjacent to the edge device.

### Claim 3 (depends on 2)

The method of claim 2, wherein a length of the shared diffusion region is greater than a length of the additional diffusion region.

### Claim 4 (depends on 3)

The method of claim 3, wherein the length of the shared diffusion region is equal to a length of another diffusion region adjacent to a first side of the edge device opposite from a second side of the edge device adjacent to the second side of the dummy device.

### Claim 5 (depends on 1)

The method of claim 1, wherein modifying the first layout resulting in the second layout further comprises:
removing a first dummy gate structure next to the dummy gate structure.

### Claim 6 (depends on 5)

The method of claim 5, wherein modifying the first layout resulting in the second layout further comprises:
removing a second dummy gate structure, so that the dummy gate structure corresponds to a single dummy gate structure next to the dummy device.

### Claim 7 (depends on 1)

The method of claim 1, further comprising deactivating the dummy device.

### Claim 8 (depends on 1)

The method of claim 1, wherein a gate structure of the edge device has a first gate length, and the dummy gate structure has a second gate length different from the first gate length.

### Claim 9 (depends on 8)

The method of claim 8, wherein the gate structure of the dummy device has a third gate length equal to the first gate length or the second gate length.

### Claim 10 (depends on 1)

The method of claim 1, wherein extending the shared diffusion region to at least the dummy device comprises:
extending the shared diffusion region to at least a first side of the dummy device, the first side of the dummy device being closer to the edge device than a second side of the dummy device away from the edge device.

### Claim 11

A method of fabricating an integrated circuit, comprising:
identifying neighboring gate structures having different gate lengths, the neighboring gate structures being part of a first layout including gate structures and diffusion regions, and the neighboring gate structures including a first gate structure having a first gate length and a second gate structure having a second gate length different from the first gate length;
modifying the first layout resulting in a second layout comprising:
inserting a dummy device between the first gate structure and the second gate structure;
extending a first diffusion region of the first gate structure to the dummy device, the first diffusion region being shared by the dummy device and the first gate structure; and
performing a design rule check on the second layout, the performing the design rule check comprises considering the sharing of the first diffusion region by the dummy device and the first gate structure as complying with a design rule of the design rule check; and
fabricating the integrated circuit based on the second layout.

### Claim 12 (depends on 11)

The method of claim 11, wherein the dummy device has the first gate length or the second gate length.

### Claim 13 (depends on 11)

The method of claim 11, wherein modifying the first layout resulting in the second layout further comprises:
extending a second diffusion region of the second gate structure to the dummy device, the second diffusion region being shared by the dummy device and the second gate structure, the first diffusion region having a first width, and the second diffusion region having a second width different from the first width.

### Claim 14 (depends on 13)

The method of claim 13, wherein performing the design rule check on the second layout further comprises:
considering the sharing of the second diffusion region by the dummy device and the second gate structure as complying with the design rule of the design rule check.

### Claim 15 (depends on 11)

The method of claim 11, wherein modifying the first layout resulting in the second layout further comprises:
adding a second diffusion region between the dummy device and a third diffusion region of the second gate structure, the second diffusion region and the third diffusion region being shared by the dummy device and the second gate structure, and the first diffusion region and the second diffusion region having a same width.

### Claim 16 (depends on 15)

The method of claim 15, wherein performing the design rule check on the second layout further comprises:
considering the sharing of the second diffusion region and the third diffusion region by the dummy device and the second gate structure as complying with the design rule of the design rule check.

### Claim 17

A method of fabricating an integrated circuit, comprising:
identifying a first device, the first device being part of a first layout including gate structures and diffusion regions, the first device having a first gate structure and an irregular diffusion region, the first device being adjacent to a second device having a second gate structure;
modifying the first layout resulting in a second layout comprising:
inserting a dummy device between the first gate structure and the second gate structure, wherein a first diffusion region is shared by the dummy device and the first gate structure, a second diffusion region is shared by the dummy device and the second gate structure, the first diffusion region or the second diffusion region has a rectangular shape, and the irregular diffusion region has a non-rectangular shape; and
performing a design rule check on the second layout, the performing the design rule check comprises considering the sharing of the first diffusion region by the dummy device and the first gate structure or the sharing of the second diffusion region by the dummy device and the second gate structure as complying with a design rule of the design rule check; and
fabricating the integrated circuit based on the second layout.

### Claim 18 (depends on 17)

The method of claim 17, wherein modifying the first layout resulting in the second layout further comprises:
extending the first diffusion region of the first gate structure to at least a first side of the dummy device; and
adding a third diffusion region between the second diffusion region of the second gate structure and a second side of the dummy device opposite from the first side,
wherein the third diffusion region has a first width, and the second diffusion region has a second width different from the first width.

### Claim 19 (depends on 17)

The method of claim 17, further comprising deactivating the dummy device.

### Claim 20 (depends on 17)

The method of claim 17, wherein modifying the first layout resulting in the second layout further comprises:
extending the first diffusion region of the first gate structure to the dummy device; and
extending the second diffusion region of the second gate structure to the dummy device.