# US 2020/0394337 A1 · Electronic circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2020/0394337 A1
- Document ID: US20200394337A1
- Status: Published application
- Kind: A1
- Application number: 16/894,523
- Filed: 2020-06-05
- Published: 2020-12-17
- Earliest claimed: 2019-06-11
- Assignees: STMicroelectronics (Rousset) SAS
- Applicants: Stmicroelectronics (Rousset) SAS
- Inventors: Fabrice MARINET
- Web page: https://patentgrep.com/patent/US20200394337A1

## CPC

- G06F 21/72: in cryptographic circuits
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- B41J 2/17546: {electronically}
- G06F 9/4498: {Finite state machines}
- G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories
- G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C 29/16: using microprogrammed units, e.g. state machines
- G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence)
- G11C 29/38: Response verification devices
- H04L 9/0631: {Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms}
- G11C 2029/0409: {Online test}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- H04L 2209/26: Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

An electronic circuit includes an interface, a read-only memory in which encrypted data are stored, and cryptographic circuitry coupled to the interface. In operation, the cryptographic circuitry uses a decryption key received via the interface to decrypt the encrypted data. The electronic circuit performs one or more operations using the decrypted data.

## Claims

### Claim 1

An electronic circuit, comprising:
an interface, which, in operation, receives a decryption key;
a read-only memory in which encrypted data are stored; and
cryptographic circuitry coupled to the interface, which, in operation, uses the decryption key received via the interface to decrypt the encrypted data, wherein, in operation, the electronic circuit performs one or more operations using the decrypted data.

### Claim 2 (depends on 1)

The electronic circuit according to claim 1 wherein the cryptographic circuitry comprises a finite-state machine.

### Claim 3 (depends on 2)

The electronic circuit according to claim 2 wherein the decryption key is supplied to the finite-state machine via the interface.

### Claim 4 (depends on 3)

The electronic circuit according to claim 3 wherein the decryption key is supplied to the finite-state machine during an activation phase.

### Claim 5 (depends on 3)

The electronic circuit according to claim 3 wherein the data are decrypted by the finite-state machine.

### Claim 6 (depends on 1)

The electronic circuit according to claim 1, comprising a non-volatile memory.

### Claim 7 (depends on 1)

The electronic circuit according to claim 1, comprising a volatile memory.

### Claim 8 (depends on 7)

The electronic circuit according to claim 7 wherein the cryptographic circuitry, in operation, stores the decrypted data in the volatile memory.

### Claim 9 (depends on 8)

The electronic circuit according to claim 8, comprising a non-volatile memory, wherein the data are stored in the volatile memory before being stored in the non-volatile memory.

### Claim 10 (depends on 1)

The electronic circuit according to claim 1 wherein the data are encrypted by an algorithm of the “Advanced Encryption Standard” (AES) type.

### Claim 11 (depends on 1)

The electronic circuit of claim 1, comprising one or more processing cores, wherein the one or more operations include a start-up operation of the one or more processing cores.

### Claim 12 (depends on 1)

The electronic circuit of claim 1, wherein, prior to the receipt of the decryption key in operation,
the decryption key is not stored in the electronic circuit; and
information from which the decryption key may be generated is not stored in the electronic circuit.

### Claim 13

A method, comprising:
receiving, by an electronic device, a decryption key via an interface of the electronic device;
decrypting, using the decryption key, encrypted data stored in a read-only memory of the electronic device; and
performing, by the electronic device, one or more operations using the decrypted data, wherein the decryption key is not stored in the electronic device prior to receipt of the decryption key via the interface.

### Claim 14 (depends on 13)

The method of claim 13, comprising receiving the decryption key during an activation phase of the electronic device.

### Claim 15 (depends on 13)

The method of claim 13, comprising storing the decrypted data in a volatile memory of the electronic device.

### Claim 16 (depends on 13)

The method of claim 13 wherein the one or more operations include a start-up operation of the electronic device.

### Claim 17 (depends on 13)

The method of claim 13, comprising:
coupling, via the interface, the electronic device to another electronic device; and
receiving the decryption key via the interface from the another electronic device, wherein the one or more operations comprise authenticating a compatibility of the electronic device and the another electronic device.

### Claim 18 (depends on 13)

The method of claim 13, wherein, prior to the receipt of the decryption key,
not storing the decryption key in the electronic device; and
not storing information from which the decryption key may be generated in the electronic device.

### Claim 19

A system, comprising:
a first electronic device; and
a second electronic device coupled to the first electronic device, the second electronic device including:
a read-only memory in which encrypted data are stored; and
cryptographic circuitry coupled to the read-only memory, which, in operation, uses a decryption key received from the first electronic device to decrypt the encrypted data, wherein, in operation, the second electronic device performs one or more operations using the decrypted data.

### Claim 20 (depends on 19)

The system of claim 19, wherein the first electronic device, in operation, provides the decryption key to the second electronic device during an activation phase of the second electronic device.

### Claim 21 (depends on 19)

The system of claim 19 wherein the one or more operations comprise authenticating a compatibility of the first and second electronic devices.

### Claim 22 (depends on 19)

The system of claim 19 wherein the first electronic device is a printer and the second electronic device is a printer cartridge.

### Claim 23 (depends on 19)

The system of claim 19, wherein, prior to the receipt of the decryption key in operation,
the decryption key is not stored in the second electronic circuit; and
information from which the decryption key may be generated is not stored in the second electronic circuit.