# US 2020/0394151 A1 · High performance interconnect > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0394151 A1 - Document ID: US20200394151A1 - Status: Published application - Kind: A1 - Application number: 17/008,363 - Filed: 2020-08-31 - Published: 2020-12-17 - Earliest claimed: 2017-03-03 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Zuoguo Wu; Debendra Das Sharma; Mohiuddin M. Mazumder; Jong-Ru Guo; Anupriya Sriramulu; Narasimha Lanka; Timothy Wig; Jeff Morriss - Web page: https://patentgrep.com/patent/US20200394151A1 ## CPC - G06F 15/17343: {wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture (reconfigurable processors arrays G06F15/7867)} - G06F 9/28: Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel - G06F 15/16: Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs {(coordinating program control therefor G06F9/52; in regulating and control system G05B)} - G06F 15/173: using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake - H03K 19/17736: Structural details of routing resources - H10W 20/01: {Manufacture or treatment} - H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number. ## Claims ### Claim 1 An apparatus comprising: a port to couple to a device over an interconnect, wherein the port comprises protocol circuitry to: send a particular training sequence on the interconnect in association with training of a link on the interconnect, wherein the link is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol, the sent training sequence is a TS2-type training sequence based on the PCIe-based protocol, TS2-type training sequences are to comprise a set of symbols and a particular one of the set of symbols comprises bits to identify whether a number of retimers are present on the link; receive a training sequence on the interconnect during the training of the link, wherein the received training sequence is also a TS2-type training sequence, the bits in the particular symbol of the received training sequence indicate a particular number of retimers present on the link, wherein the particular number of retimers are positioned between the port and the device on the interconnect; and participate in equalization of the link, wherein the equalization of the link is based on the particular number of retimers present on the link. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the protocol circuitry is to train the link to operate at a speed of 16.0 gigatransfers/second (GT/s). ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the PCIe-based protocol comprises PCIe Generation 4.0. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the particular symbol comprises symbol 5 of the TS2-type training sequence. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the received training sequence is responsive to the sent training sequence. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the particular number of retimers comprises zero, one, or two retimers. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the protocol circuitry is further to send a SKP ordered set (SKP OS) on the link, and the SKP OS is to be used to perform clock compensation for the link. ### Claim 8 An apparatus comprising: a retimer to extend a physical length of a link, wherein the link is to couple a first device to a second device, and the retimer is to be positioned between the first device and second device on the link, wherein the link is compliant with a PCIe-based protocol, and the retimer comprises protocol circuitry to: receive a first TS2 training sequence sent by the first device on a first link segment of the link, wherein the first link segment connects the first device to the retimer, the first TS2 training sequence comprises a particular symbol, and the particular symbol comprises a set of bits to identify presence of retimers on the link; regenerate the first TS2 training sequence to forward to the second device on a second link segment of the link, wherein the second link segment connects the retimer to the second device, and the first TS2 training sequence is regenerated to include a value in the set of bits to identify presence of the retimer on the link; send the regenerated first TS2 training sequence to the second device on the second link segment; and participate in an equalization of the link based on the PCIe-based protocol. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the particular symbol comprises symbol 5 of the first TS2 training sequence. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the protocol circuitry is further to: receive a second TS2 training sequence from the second device over the second link segment, wherein the second TS2 training sequence comprises the particular symbol; and forward the second TS2 training sequence to the first device over the first link segment, wherein the second TS2 training sequence is a looped-back version of the first TS2 training sequence. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the protocol circuitry is further to regenerate the second TS2 training sequence to include a particular value in the set of bits of the particular symbol in the second TS2 training sequence to identify presence of the retimer, and the regenerated second TS2 training sequence is forwarded to the first device. ### Claim 12 (depends on 8) The apparatus of claim 8, wherein the equalization comprises transmitter equalization at the retimer. ### Claim 13 (depends on 8) The apparatus of claim 8, wherein the protocol circuitry is further to: receive an ordered set from the first device on the first link segment; and identify that the ordered set comprises a SKP ordered set (SKP OS) based on the PCIe-based protocol. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the protocol circuitry is further to remove a symbol from the SKP OS to perform clock compensation for the link. ### Claim 15 A system comprising: a first device; a second device; and a retimer, wherein the first device and the second device are coupled by a physical interconnect, the retimer is positioned between the first device and the second device on the interconnect, the retimer is to extend the physical length of a link to be established on the interconnect, and the retimer comprises protocol circuitry to: receive a training sequence on a first link segment formed on the interconnect to physically couple the first device to the retimer, the training sequence has a TS2 training sequence format, and the TS2 training sequence format comprises a particular symbol and the particular symbol comprises a set of bits defined to identify retimers present on the link; set a value in the set of bits to identify presence of the retimer on the link; forward the training sequence to the second device on a second link segment, wherein the training sequence forwarded to the second device comprises the value in the set of bits, and the second link segment physically connects the retimer to the second device; receive a SKP ordered set (SKP) from the first device; and remove symbols from the SKP OS to perform clock compensation for the link, wherein the retimer is to forward the SKP OS with the removed symbols to the second device. ### Claim 16 (depends on 15) The system of claim 15, wherein the TS2 training sequence format is defined according to a Peripheral Component Interconnect Express (PCIe)-based protocol. ### Claim 17 (depends on 16) The system of claim 16, wherein the particular symbol comprises symbol 5 of a PCIe TS2 training sequence. ### Claim 18 (depends on 16) The system of claim 16, wherein the PCIe-based protocol comprises PCIe 4.0. ### Claim 19 (depends on 15) The system of claim 15, wherein one of the first device or the second device comprises an accelerator device. ### Claim 20 (depends on 15) The system of claim 15, wherein one of the first device or the second device comprises a memory device. ### Claim 21 (depends on 15) The system of claim 15, wherein one of the first device or the second device comprises a graphics device. ### Claim 22 (depends on 15) The system of claim 15, wherein one of the first device or the second device comprises a network controller.