Semi-Additive Process for Printed Circuit Boards
AssigneeCatlam, LLC
InventorsKenneth S. BAHL, Konstantine KARAVAKIS
Life of this patent
Estimating the term…
Abstract
A circuit board has a dielectric core, a foil top surface, and a thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.
Claims21
1) A process for forming fine pitch dot vias on a laminate having a bottom thin foil bonded to the laminate, a comparatively thicker backing foil adjacent to the bottom thin foil, and an optional thin top foil, the process comprising:
- laser drilling blind vias through the laminate top surface to the bottom thin foil, optionally also drilling through holes penetrating through the laminate, bottom thin foil, and backing foil;
- removing the backing foil;
- treating the surfaces of the laser drilled vias and drilled holes with a catalyst;
- electroless plating the optional top foil surface and bottom foil surface, the inner surfaces of the vias, and the inner surfaces of the optionally drilled through holes;
- applying patterned resist over the top and bottom surface;
- electro-plating the circuit board until copper is deposited to a level below the patterned resist;
- tin plating the exposed copper regions of the circuit board;
- stripping the patterned resist;
- quick etching the exposed copper regions to the underlying laminate;
- optionally etching the tin plating.
10) A process for forming vias and traces on a circuit board comprising a catalytic laminate having a bottom thin foil bonded to the catalytic laminate, a comparatively thicker removable backing foil applied to the bottom thin foil, and an optional top foil, the catalytic laminate having particles of catalyst enabling electroless plating on surfaces which have been drilled, the process comprising:
- laser drilling blind vias through the catalytic laminate top surface to the bottom thin foil without penetrating the bottom thin foil, optionally also drilling through holes penetrating the laminate, bottom thin foil, and bottom backing foil;
- removing the bottom backing foil;
- electroless plating the bottom thin foil, optional top foil, via surfaces, and through hole surfaces to form an electrically continuous conductive layer;
- applying patterned resist to the top surface and bottom surface;
- electro-plating the circuit board until copper is deposited on exposed copper areas to a level below the patterned resist;
- tin plating the exposed copper regions of the circuit board;
- stripping the patterned resist;
- etching the exposed copper regions until the electroplated copper and underlying thin foil is removed;
- optionally etching the tin plating;
- optionally laminating additional dielectric layers and foil layers to the top or bottom surface of the circuit board.
15) A process for forming a multi-layer board having an inner core and one or more pairs of outer layers,
- said inner core formed on a dielectric having a thin top foil applied to the top surface of the dielectric, the thin top foil opposite surface optionally having a removable comparatively thicker backing foil, the dielectric bottom surface having a thin bottom foil applied, the thin bottom foil opposite surface in contact with a comparatively thicker removable backing foil, the inner core formed by:
- laser drilling at least one via through the dielectric to the depth of the thin bottom foil without penetrating the thin bottom foil, optionally drilling at least one through hole,
- said laser drilled vias and optional thru holes having surfaces with exposed catalytic particles;
- thereafter electroless plating exposed catalytic particles and said top thin copper foil and said thin bottom copper foil;
- thereafter applying patterned resist to create exposed copper areas and concealed copper areas;
- thereafter electroplating said exposed copper areas;
- thereafter tin plating said exposed copper areas;
- thereafter stripping said patterned resist;
- thereafter quick etching the inner core until the previously concealed copper areas are etched free of copper;
- said outer layer pairs formed by applying a dielectric layer to each side of the inner core, the opposite surface of each dielectric layer having a thin foil, for each outer layer pair:
- laser drilling at least one via and optional thru holes through the dielectric layer to an underlying copper layer;
- the laser drilled holes having exposed catalytic particles;
- electroless plating the exposed thin copper foil and exposed catalytic particles;
- applying patterned resist to at least one surface;
- electroplating the exposed surfaces;
- plating tin onto the electroplated areas;
- stripping the patterned resist;
- quick etching the exposed copper.
20) A process for forming a circuit board core, the circuit board core having a catalytic laminate with a thin foil laminated on a bottom surface, the thin foil being adjacent to a thick backing foil;
- forming vias in the top surface of the catalytic laminate which reach the thin foil but do not penetrate the thin foil, the thick backing foil being sufficiently thick to prevent melting the thin foil, also forming trace channels in the top surface of the catalytic laminate, the trace channels having sufficient depth to expose underlying catalytic particles in the catalytic laminate;
- removing the thick backing foil;
- electroless plating the exposed copper surfaces and catalytic laminate in regions with exposed catalytic particles;
- applying a blanket resist mask to the entire top surface and a patterned resist mask to the bottom surface;
- etching the exposed regions of the bottom surface which are not covered by resist mask;
- stripping the resist mask.
21) A process for forming a multi-layer circuit board from a central core having filled vias and traces, the process comprising:
- laminating a catalytic laminate to each surface of the central core;
- forming channels in the outer surfaces of the catalytic laminate which expose underlying catalytic particles, and also forming vias which are concentric to the axis of an underlying via, the vias formed in the catalytic laminate exposing the underlying filled via;
- electroless plating the catalytic laminate, thereby forming traces in the channels and filling the vias in the catalytic laminate so they are electrically continuous with the core filled via.
Dependencies are inferred from the claim text.