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US 2020/0356699 A1Published application
Security plugin for a system-on-a-chip platform
AssigneeIntel Corporation
InventorsManoj R. Sastry, Alpa Narendra Trivedi, Men Long
Life of this patent
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Abstract
Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.
Claims17
A system comprising:
- a first chip including:
- a first plurality of chip components, at least some of the first plurality of chip components to send component messages to a second chip;
- a first fabric coupling the first plurality of chip components with one another, the first fabric to transmit the component messages in the first chip;
- a first interconnect endpoint coupled with the first fabric, the first interconnect endpoint to interface the first plurality of chip components to an inter-chip interconnect, the first interconnect endpoint including:
- a first interconnect interface, the first interconnect interface to receive the component messages;
- a first security component coupled with the first interconnect interface, wherein the first interconnect interface makes the first security component available to the first plurality of chip components for the component messages sent to the first interconnect endpoint, the first security component including:
- a first cryptographic engine to receive and encrypt the component messages to create encrypted component messages;
- and
- a first integrity engine to compute integrity elements associated with the component messages;
- and
- a first interconnect packager coupled with the first security component, the first interconnect packager to produce interconnect messages based on the encrypted component messages and the integrity elements, the interconnect messages structured to conform to messaging of the inter-chip interconnect;
- a cryptographic controller to manage a plurality of cryptographic keys, and wherein the cryptographic controller is to perform key negotiation with another component;
- and
- a state manager to manage cryptographic sessions associated with the first chip, wherein the state manager is to maintain a first data structure, the first data structure to include a field for a session key;
- the inter-chip interconnect coupled with the first chip, the inter-chip interconnect to transmit the interconnect messages according to the messaging of the inter-chip interconnect, wherein the interconnect messages being based on the encrypted component messages and the integrity elements provide secrecy and integrity protection to the interconnect messages during the transmission on the inter-chip interconnect;
- and
- the second chip coupled with the inter-chip interconnect, the second chip including:
- a second interconnect endpoint including:
- a second interconnect packager coupled with the inter-chip interconnect, the second interconnect packager to convert the interconnect messages back into the encrypted component messages and the integrity elements;
- a second security component coupled with the second interconnect packager, the second security component including:
- a second integrity engine to verify integrity associated with the component messages using the integrity elements;
- and
- a second cryptographic engine, wherein the second security component is to decrypt the encrypted component messages back to the component messages;
- and
- a second interconnect interface, the second interconnect interface to receive the component messages;
- a second fabric coupled with the second interconnect interface, the second fabric to transmit the component messages in the second chip;
- and
- a second plurality of chip components coupled with the second fabric, at least one of the second plurality of chip components to receive the component messages.
25 more elements
A system comprising:
- a first chip including:
- a first plurality of chip components, at least some of the first plurality of chip components to send component messages to a second chip, wherein the first plurality of chip components include a plurality of processors, a memory management component, an input/output component, and a plurality of sensors;
- a first fabric coupling the first plurality of chip components with one another, the first fabric to transmit the component messages in the first chip;
- and
- a first interconnect endpoint coupled with the first fabric, the first interconnect endpoint to interface the first plurality of chip components to an inter-chip interconnect, the first interconnect endpoint including:
- a first interconnect interface, the first interconnect interface to receive the component messages;
- a first security component coupled with the first interconnect interface, wherein the first interconnect interface makes the first security component available to the first plurality of chip components for the component messages sent to the first interconnect endpoint, the first security component including:
- a first cryptographic engine to receive and encrypt the component messages to create encrypted component messages;
- and
- a first integrity engine to compute integrity elements associated with the component messages;
- and
- a first interconnect packager coupled with the first security component, the first interconnect packager to produce interconnect messages based on the encrypted component messages and the integrity elements, the interconnect messages structured to conform to a messaging technique of the inter-chip interconnect;
- the inter-chip interconnect coupled with the first chip, the inter-chip interconnect to transmit the interconnect messages according to the messaging technique, wherein the interconnect messages being based on the encrypted component messages and the integrity elements provide secrecy and integrity protection to the interconnect messages during the transmission on the inter-chip interconnect;
- and
- the second chip coupled with the inter-chip interconnect, the second chip including:
- a second interconnect endpoint including:
- a second interconnect packager coupled with the inter-chip interconnect, the second interconnect packager to convert the interconnect messages back into the encrypted component messages and the integrity elements;
- a second security component coupled with the second interconnect packager, the second security component including:
- a second integrity engine to verify integrity associated with the component messages using the integrity elements;
- and
- a second cryptographic engine, wherein the second security component is to decrypt the encrypted component messages back to the component messages;
- and
- a second interconnect interface, the second interconnect interface to receive the component messages;
- a second fabric coupled with the second interconnect interface, the second fabric to transmit the component messages in the second chip;
- and
- a second plurality of chip components coupled with the second fabric, at least one of the second plurality of chip components to receive the component messages.
23 more elements
Dependencies are inferred from the claim text.