Method and apparatus for flexible and efficient analytics in a network switch
AssigneeCavium International
InventorsWeihuang Wang, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
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Abstract
Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
Claims30
1-25. (canceled)
An analytics bank comprising:
- at least three processing units including:
- a counter processing unit;
- a policing processing unit, wherein the policing processing unit is able to push a request to another analytics bank for byte counting of color, wherein the another analytics bank is immediately next to the analytics bank;
- and
- a sampling processing unit;
- and
- a memory bypass module to hide memory read latency, wherein output data of the memory bypass module is directed to the counter processing unit, the policing processing unit or the sampling processing unit.
29-35. (canceled)
An analytics bank pair comprising:
- a first analytics bank;
- and
- a second analytics bank immediately adjacent to the first analytics bank within a common memory pool, each of the first analytics bank and the second analytics bank comprising a counter processing unit, a policing processing unit and a sampling processing unit, wherein when the first analytics bank is configured in policing mode and the second analytics bank is configured in counting mode, the policing processing unit of the first analytics bank sends a counter request to the counter processing unit of the second analytics bank to calculate byte count for a packet in each color.
An analytics bank comprising:
- at least two processing units selected from the group consisting of a counter processing unit, a policing processing unit and a sampling processing unit;
- and
- a memory bypass module to hide memory read latency, wherein output data of the memory bypass module is directed to the counter processing unit, the policing processing unit or the sampling processing unit such that the analytics bank is able to be switched from one of counting with the counter processing unit, policing with the policing processing unit and sampling with the sampling processing unit to another of the counting with the counter processing unit, the policing with the policing processing unit and the sampling with the sampling processing unit by switching where the output data of the memory bypass module is directed.
Dependencies are inferred from the claim text.