Back to results
US 2020/0350366 A1Published application
Techniques for mram top electrode via connection
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
Life of this patent
Estimating the term…
Abstract
Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.
Claims20
An integrated chip, comprising:
- a first memory cell overlying a substrate;
- a second memory cell overlying the substrate;
- a dielectric structure overlying the substrate, wherein a trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell;
- and
- a dielectric layer disposed within the trench.
2 more elements
An integrated chip, comprising:
- a first memory cell overlying a substrate;
- a first inter-level dielectric (ILD) layer overlying and laterally surrounding the first memory cell;
- and
- a first dielectric layer overlying the first ILD layer, wherein the first dielectric layer extends along a top surface of the first ILD layer and comprises a first protrusion that extends below the top surface of the first ILD layer.
1 more element
An integrated chip, comprising:
- a memory cell disposed within an interconnect structure;
- an inter-level dielectric (ILD) layer (140) overlying and laterally enclosing the memory cell, wherein the ILD layer comprises sidewalls defining a trough;
- a conductive structure overlying the memory cell and disposed within the ILD layer, wherein a top surface of the conductive structure is aligned with a top surface of the ILD layer;
- and
- a dielectric layer disposed within the trough, wherein a bottom surface of the dielectric layer is disposed below the top surface of the conductive structure.
2 more elements
Dependencies are inferred from the claim text.