Vertical memory devices

A vertical memory device, comprising:

• a substrate including single crystalline silicon;
• an insulating buffer layer on a lower surface of the substrate;
• a semiconductor plate on a lower surface of the insulating buffer layer, the semiconductor plate including silicon;
• gate electrodes spaced apart from each other under the semiconductor plate in a first direction substantially perpendicular to a lower surface of the substrate, the gate electrodes being arranged to have a staircase shape of which extension lengths of the gate electrodes in a second direction substantially parallel to the lower surface of the substrate gradually decrease from an uppermost level toward a lowermost level;
• a channel structure extending through the gate electrodes in the first direction, the channel structure having a width gradually increasing from a top toward a bottom thereof, and the channel structure including:
• a first channel contacting a lower surface of the semiconductor plate;
• and
• a second channel contacting a lower surface of the first channel;
• a bit line under the channel structure, the bit line being electrically connected to the channel structure;
• a gate structure disposed on the substrate;
• an impurity region disposed at an upper portion of the substrate adjacent to the gate structure;
• and
• a first contact plug extending in the first direction on the impurity region to contact the impurity region.

A vertical memory device, comprising:

• a substrate including single crystalline silicon;
• an insulating buffer layer on a lower surface of the substrate;
• a semiconductor plate on a lower surface of the insulating buffer layer;
• first gate electrodes spaced apart from each other under the semiconductor plate in a first direction substantially perpendicular to the lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level;
• second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level;
• and
• a channel structure extending through the first and second gate electrodes in the first direction.