Layout modification method for exposure manufacturing process

A layout modification method for fabricating a semiconductor device, comprising:

• dividing a patterned layer of a layout into a first portion and a second portion for an exposure manufacturing process to produce the semiconductor device, wherein a width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process;
• measuring uniformity of critical dimension of the patterned layer;
• and
• adjusting the critical dimension of the second portion of the patterned layer according to the uniformity of critical dimension to generate a modified layout,
• wherein the first portion of the patterned layer is surrounded by the second portion of the patterned layer.

A non-transitory computer-readable medium containing instructions which, when executed by a processor of a computer system, cause the processor to execute a layout modification method for fabricating a semiconductor device, comprising:

• calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce the semiconductor device, wherein the patterned layer is divided into a first portion and a second portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process, wherein the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process;
• and
• compensating the critical dimension of the second portion of the patterned layer according to the uniformity of critical dimensions to generate a modified layout,
• wherein the patterned layer comprises a plurality of absorbers, and the number of the absorbers in the first portion of the patterned layer is greater than that in the second portion of the patterned layer.