US 2020/0350293 A1 · SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES

Abstract

Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.

Claims20

Dependent claims

1-20. (canceled)

A semiconductor device, comprising:

a redistribution structure having an upper surface and a lower surface opposite the upper surface, wherein the redistribution structure does not include a pre-formed substrate between the upper and lower surfaces;
a first semiconductor die coupled to the redistribution structure and having an upper surface facing away from the redistribution structure, wherein the upper surface of the first semiconductor includes first bond pads;
first wire bonds electrically coupling the first bond pads of the first semiconductor die to the redistribution structure;
a second semiconductor die having a lower surface facing the redistribution structure and an upper surface facing away from the redistribution structure, wherein the lower surface of the second semiconductor die is coupled to the upper surface of the first semiconductor die, wherein the second semiconductor die extends laterally beyond at least one side of the first semiconductor die to define an overhang portion of the second semiconductor die, and wherein the lower surface of the second semiconductor die includes second bond pads at the overhang portion;
conductive features electrically coupling the second bond pads of the second semiconductor die to the redistribution structure;
a third semiconductor die having a lower surface facing the redistribution structure and an upper surface facing away from the redistribution structure, wherein all of the lower surface of the third semiconductor die is positioned over and coupled to the upper surface of the second semiconductor die, and wherein the upper surface of the third semiconductor die includes third bond pads;
and
second wire bonds electrically coupling the third bond pads of the third semiconductor die to the redistribution structure.

5 more elements

A semiconductor device, comprising:

a redistribution structure having an upper surface and a lower surface opposite the upper surface, wherein the redistribution structure does not include a pre-formed substrate between the upper and lower surfaces;
a first semiconductor die coupled to the redistribution structure and having an upper surface facing away from the redistribution structure, wherein the upper surface of the first semiconductor includes first bond pads;
first wire bonds electrically coupling the first bond pads of the first semiconductor die to the redistribution structure;
a second semiconductor die having a lower surface facing the redistribution structure and an upper surface facing away from the redistribution structure, wherein the lower surface of the second semiconductor die is coupled to the upper surface of the first semiconductor die, wherein the second semiconductor die extends in a direction laterally beyond at least one side of the first semiconductor die to define an overhang portion of the second semiconductor die, and wherein the lower surface of the second semiconductor die includes second bond pads at the overhang portion;
first conductive columns electrically coupling the second bond pads of the second semiconductor die to the redistribution structure;
a third semiconductor die having a lower surface facing the redistribution structure and an upper surface facing away from the redistribution structure, wherein all of the lower surface of the third semiconductor die is positioned over and coupled to the upper surface of the second semiconductor die, and wherein the upper surface of the third semiconductor die includes third bond pads;
second wire bonds electrically coupling the third bond pads of the third semiconductor die to the redistribution structure;
a fourth semiconductor die having a lower surface facing the redistribution structure and an upper surface facing away from the redistribution structure, wherein the lower surface of the fourth semiconductor die is coupled to the upper surface of the third semiconductor die, wherein the fourth semiconductor die extends laterally in the direction beyond at least one side of the third semiconductor die to define an overhang portion of the fourth semiconductor die, and wherein the lower surface of the fourth semiconductor die includes fourth bond pads at the overhang portion of the fourth semiconductor die;
and
second conductive columns electrically coupling the fourth bond pads of the fourth semiconductor die to the redistribution structure.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/933,649Filed 20 Jul 2020

Priority

24 Aug 2017

Published

5 Nov 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification42 codes

H10W 90/00
Package configurations
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 72/20
Interconnections or connectors in packages: bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
H10P 72/7424
Using temporarily an auxiliary support: used as a support during the manufacture of self-supporting substrates

Semiconductor device having laterally offset stacked semiconductor dies

Life of this patent

Semiconductor device having laterally offset stacked semiconductor dies

Life of this patent

Abstract

Claims20