Memory device

A memory device comprising:

• a first memory cell array including a plurality of first electrode layers, a first conductive layer, and a first semiconductor pillar,
• the first electrode layers being stacked in a first direction,
• the first conductive layer being provided above the first electrode layers in the first direction,
• the first semiconductor pillar extending through the first electrode layers in the first direction, the first semiconductor pillar being connected to the first conductive layer;
• a first contact plug extending in the first direction through the first electrode layers, the first contact plug being connected to the first conductive layer;
• a second memory cell array provided above the first memory cell array in the first direction, the second memory cell array including a plurality of second electrode layers, a second conductive layer, and a second semiconductor pillar,
• the second electrode layers being stacked in the first direction,
• the second conductive layer being provided above the second electrode layers in the first direction,
• the second semiconductor pillar extending in the first direction through the second electrode layers, the second semiconductor pillar being connected to the second conductive layer;
• a second contact plug extending in the first direction through the second electrode layers, the second contact plug being connected to the second conductive layer;
• and
• a connection metal provided between the first and second memory cell arrays, the connection metal electrically connecting the first contact plug and the second conductive layer.