Semiconductor device, method for fabricating the semiconductor device, and memory device and system including the semiconductor device

A memory device comprising:

• a stack structure formed in a cell array region and a contact region and comprising a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, in which the stack structure has a stepped structure such that any one of the first conductive patterns in the contact region further protrudes than the first conductive pattern positioned immediately above it;
• a channel pillar which passes through the stack structure of the cell array region;
• a memory layer which is interposed between the channel pillar and the first conductive patterns;
• a plurality of second conductive patterns which are respectively formed over protrusions of the plurality of first conductive patterns in the contact region;
• a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure;
• and
• a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.

A system comprising:

• a memory device for storing data;
• a host accessing the data stored in the memory device;
• and
• a controller for controlling the memory device in response to a request of the host between the host and the memory device,
• wherein the memory device includes:
• a stack structure formed in a cell array region and a contact region and comprising a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, in which the stack structure has a stepped structure such that any one of the first conductive patterns in the contact region further protrudes than the first conductive pattern positioned immediately above it;
• a channel pillar which passes through the stack structure of the cell array region;
• a memory layer which is interposed between the channel pillar and the first conductive patterns;
• a plurality of second conductive patterns which are respectively formed over protrusions of the plurality of first conductive patterns in the contact region;
• a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure;
• and
• a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.